Nowadays Embedded Systems require high performance specific
computations, usually with real-time and Quality of Service
constraints, which should run at a low energy level to extend
battery life and avoid heating. Very Long Instruction Word (VLIW)
processors are a good solution providing enough computational
performance at low power with the required programmability to meet
short time-to-market restrictions. For those architectures with a
high number of computational resources running in parallel the
access to data is becoming the main bottleneck that limits the
available parallelism. The purpose of this work is to prove that
optimizing address generation is an effective of accessing data
while decreasing execution time and energy consumption. First, this
work evaluates the effectiveness of VLIW processors and presents
the architectural exploration framework used for the experiments.
It also presents a systematic classification of address generators,
a review of literature according to the classification of the
different optimizations on the address generation process and a
step-wise methodology that gradually reduces energy.
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