This book presents a new exploration environment for mesh-based,
heterogeneous FPGA architectures. It describes state-of-the-art
techniques for reducing area requirements in FPGA architectures,
which also increase performance and enable reduction in power
required. Coverage focuses on reduction of FPGA area by introducing
heterogeneous hard-blocks (such as multipliers, adders etc) in
FPGAs, and by designing application specific FPGAs. Automatic FPGA
layout generation techniques are employed to decrease non-recurring
engineering (NRE) costs and time-to-market of application-specific,
heterogeneous FPGA architectures.
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