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Timing Optimization Through Clock Skew Scheduling (Hardcover, 2000 ed.)
Loot Price: R2,987
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Timing Optimization Through Clock Skew Scheduling (Hardcover, 2000 ed.)
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History of the Book The last three decades have witnessed an
explosive development in integrated circuit fabrication
technologies. The complexities of cur rent CMOS circuits are
reaching beyond the 100 nanometer feature size and multi-hundred
million transistors per integrated circuit. To fully exploit this
technological potential, circuit designers use sophisticated
Computer-Aided Design (CAD) tools. While supporting the talents of
innumerable microelectronics engineers, these CAD tools have become
the enabling factor responsible for the successful design and
implemen tation of thousands of high performance, large scale
integrated circuits. This research monograph originated from a body
of doctoral disserta tion research completed by the first author at
the University of Rochester from 1994 to 1999 while under the
supervision of Prof. Eby G. Friedman. This research focuses on
issues in the design of the clock distribution net work in large
scale, high performance digital synchronous circuits and
particularly, on algorithms for non-zero clock skew scheduling.
During the development of this research, it has become clear that
incorporating timing issues into the successful integrated circuit
design process is of fundamental importance, particularly in that
advanced theoretical de velopments in this area have been slow to
reach the designers' desktops."
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