This book constitutes the refereed proceedings of the 16th
International Workshop on Power and Timing Modeling, Optimization
and Simulation, PATMOS 2006. The book presents 41 revised full
papers and 23 revised poster papers together with 4 key notes and 3
industrial abstracts. Topical sections include high-level design,
power estimation and modeling memory and register files, low-power
digital circuits, busses and interconnects, low-power techniques,
applications and SoC design, modeling, and more.
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