Thanks to the advance of semiconductor and communication
technology, the wireless communication market has been booming in
the last two decades. It evolved from simple pagers to emerging
third-generation (3G) cellular phones. In the meanwhile, broadband
communication market has also gained a rapid growth. As the market
always demands hi- performance and low-cost products, circuit
designers are seeking hi- integration communication devices in
cheap CMOS technology. The phase-locked loop frequency synthesizer
is a critical component in communication devices. It works as a
local oscillator for frequency translation and channel selection in
wireless transceivers and broadband cable tuners. It also plays an
important role as the clock synthesizer for data converters in the
analog-and-digital signal interface. This book covers the design
and analysis of PLL synthesizers. It includes both fundamentals and
a review of the state-of-the-art techniques. The transient analysis
of the third-order charge-pump PLL reveals its locking behavior
accurately. The behavioral-level simulation of PLL further
clarifies its stability limit. Design examples are given to clearly
illustrate the design procedure of PLL synthesizers. A complete
derivation of reference spurs in the charge-pump PLL is also
presented in this book. The in-depth investigation of the digital
CA modulator for fractional-N synthesizers provides insightful
design guidelines for this important block.
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