Fast, Efficient and Predictable Memory Accesses - Optimization Algorithms for Memory Architecture Aware Compilation (Hardcover, 2006 ed.)

Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.

General

Imprint:	Springer-Verlag New York
Country of origin:	United States
Release date:	July 2006
First published:	2006
Authors:	Lars Wehmeyer • Peter Marwedel
Dimensions:	235 x 155 x 15mm (L x W x T)
Format:	Hardcover
Pages:	258
Edition:	2006 ed.
ISBN-13:	978-1-4020-4821-0
Categories:	Books > Computing & IT > Computer hardware & operating systems > Operating systems & graphical user interfaces (GUIs) > General
LSN:	1-4020-4821-1
Barcode:	9781402048210

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