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Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Hardcover, 2nd ed. 2007) Loot Price: R5,187
Discovery Miles 51 870
Repayment Terms: R486 pm x 12*
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Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Hardcover, 2nd ed. 2007): Manoj Sachdev, Jose Pineda De Gyvez

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Hardcover, 2nd ed. 2007)

Manoj Sachdev, Jose Pineda De Gyvez

Series: Frontiers in Electronic Testing, 34

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Loot Price R5,187 Discovery Miles 51 870 | Repayment Terms: R486 pm x 12*

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The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.

General

Imprint: Springer-Verlag New York
Country of origin: United States
Series: Frontiers in Electronic Testing, 34
Release date: June 2007
First published: June 2007
Authors: Manoj Sachdev • Jose Pineda De Gyvez
Dimensions: 235 x 155 x 20mm (L x W x T)
Format: Hardcover
Pages: 328
Edition: 2nd ed. 2007
ISBN-13: 978-0-387-46546-3
Categories: Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
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LSN: 0-387-46546-4
Barcode: 9780387465463

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