System Level Design from HW/SW to Memory for Embedded Systems - 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguacu, Brazil, November 3-6, 2015, Proceedings (Hardcover, 1st ed. 2017)

This book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguacu, Brazil, in November 2015. The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications.

General

Imprint:	Springer International Publishing AG
Country of origin:	Switzerland
Series:	IFIP Advances in Information and Communication Technology, 523
Release date:	April 2018
First published:	2017
Editors:	Marcelo Goetz • Gunar Schirner • Marco Aurelio Wehrmeister • Mohammad Abdullah Al Faruque • Achim Rettberg
Dimensions:	235 x 155mm (L x W)
Format:	Hardcover
Pages:	231
Edition:	1st ed. 2017
ISBN-13:	978-3-319-90022-3
Categories:	Books > Computing & IT > Computer hardware & operating systems > General Books > Computing & IT > Applications of computing > Artificial intelligence > Knowledge-based systems / expert systems
LSN:	3-319-90022-6
Barcode:	9783319900223

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