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Books > Computing & IT > General theory of computing
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High-Speed Clock Network Design (Hardcover, 2003 ed.)
Loot Price: R5,466
Discovery Miles 54 660
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High-Speed Clock Network Design (Hardcover, 2003 ed.)
Expected to ship within 10 - 15 working days
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High-Speed Clock Network Design is a collection of design concepts,
techniques and research works from the author for clock
distribution in microprocessors and high-performance chips. It is
organized in 11 chapters as follows. Chapter 1 provides an overview
to the design of clock networks. Chapter 2 specifies the timing
requirements in digital design. Chapter 3 shows the circuits of
sequential elements including latches and flip-flops. Chapter 4
describes the domino circuits, which need special clock signals.
Chapter 5 discusses the phase-locked loop (PLL) and delay-locked
loop (DLL), which provide the clock generation and de-skewing for
the on-chip clock distribution. Chapter 6 summarizes the clock
distribution techniques published in the state-of-the-art
microprocessor chips. Chapter 7 describes the CAD flow on the clock
network simulation. Chapter 8 gives the research work on
low-voltage swing clock distribution. Chapter 9 explores the
possibility of placing the global clock tree on the package layers.
Chapter 10 shows the algorithms of balanced clock routing and wire
sizing for the skew minimization. Chapter 11 shows a commercial CAD
tool that deals with clock tree synthesis in the ASIC design flow.
The glossary is attached at the end of this book. The clock network
design is still a challenging task in most high-speed VLSI chips,
since the clock frequency and power consumption requirements are
increasingly difficult to meet for multiple clock networks on the
chip. Many research works and industry examples will be shown in
this area to continually improve the clock distribution networks
for future high-performance chips.
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