The book is pivoted to the usage of the 2-D Discrete Cosine
Transform (DCT) technique for image compression, wherein the
readers will come across the development of a new and faster 2-D
DCT algorithm, and its hardware implementation. It describes the
evolution of VHDL codes by implementing DSP Design Architect tools
from Mentor Graphics in respect of hardware chip realization.
However, efforts are also made simultaneously towards the
development of the relevant algorithm in MATLAB platform in order
to verify the functionality of the developed VHDL codes. The
synthesis of VHDL codes using Quartus Integrated Synthesis (QIS)
tools was performed by implementing Altera's library (90-nm) to
make the synthesized design downloaded to a Field Programmable Gate
Array (FPGA) board. The synthesis software was also used to
optimize the performance of the design related features such as
chip area, delay, clock frequency and power dissipation. The book
presents the development of fast processor in a lucid fashion so
that the readers would grasp the theme presented, and be motivated
to actually realize the developed processor as well as implement
the ideas in their own designs.
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