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SystemVerilog for Design Second Edition - A Guide to Using SystemVerilog for Hardware Design and Modeling (Hardcover, 2nd ed. 2006) Loot Price: R5,959
Discovery Miles 59 590
Repayment Terms: R558 pm x 12*
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SystemVerilog for Design Second Edition - A Guide to Using SystemVerilog for Hardware Design and Modeling (Hardcover, 2nd ed....

SystemVerilog for Design Second Edition - A Guide to Using SystemVerilog for Hardware Design and Modeling (Hardcover, 2nd ed. 2006)

Stuart Sutherland; Foreword by P. Moorby; Simon Davidmann, Peter Flake

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Loot Price R5,959 Discovery Miles 59 590 | Repayment Terms: R558 pm x 12*

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SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were presented, such as two-state data types, enumerated types, user-degined types, structures, unions, and interfaces. Emphasis was placed on the proper usage of these enhancements for simulation and synthesis.

General

Imprint: Springer-Verlag New York
Country of origin: United States
Release date: July 2006
First published: August 2006
Authors: Stuart Sutherland
Foreword by: P. Moorby
Authors: Simon Davidmann • Peter Flake
Dimensions: 235 x 156 x 31mm (L x W x T)
Format: Hardcover
Pages: 418
Edition: 2nd ed. 2006
ISBN-13: 978-0-387-33399-1
Categories: Books > Computing & IT > General theory of computing > Systems analysis & design
Books > Computing & IT > Computer hardware & operating systems > General
Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > General
LSN: 0-387-33399-1
Barcode: 9780387333991

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