Advances of video coding made an adverse impact on VLSI
implementation over mobile communication systems. Those impacts
mainly include area, power, and channel deterioration in the video
decoding side. Therefore, this book presents a low- power
dual-standard video decoder to improve the area/power efficiency.
It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a
single chip and features a scalable architecture to reduce the
required silicon area as well as power dissipation. Moreover, to
combat transmission errors of video streams, this design is robust
to the channel behavior for improving the subjective and objective
visual quality.
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