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Books > Computing & IT > General theory of computing
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VLSI Planarization - Methods, Models, Implementation (Hardcover, 1997 ed.)
Loot Price: R3,065
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VLSI Planarization - Methods, Models, Implementation (Hardcover, 1997 ed.)
Series: Mathematics and Its Applications, 399
Expected to ship within 10 - 15 working days
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At the beginning we would like to introduce a refinement. The term
'VLSI planarization' means planarization of a circuit of VLSI, Le.
the embedding of a VLSI circuit in the plane by different criteria
such as the minimum number of connectors, the minimum total length
of connectors, the minimum number of over-the-element routes, etc.
A connector is designed to connect the broken sections of a net. It
can be implemented in different ways depending on the technology.
Connectors for a bipolar VLSI are implemented by diffused tun nels,
for instance. By over-the-element route we shall mean a connection
which intersects the enclosing rectangle of an element (or a cell).
The possibility of the construction such connections during circuit
planarization is reflected in element models and can be ensured,
for example, by the availability of areas within the rectangles
where connections may be routed. VLSI planarization is one of the
basic stages (others will be discussed below) of the so called
topological (in the mathematical sense) approach to VLSI design.
This approach does not lie in the direction of the classical
approach to automation of VLSI layout design. In the classical
approach to computer aided design the placement and routing
problems are solved successively. The topological approach, in
contrast, allows one to solve both problems at the same time. This
is achieved by constructing a planar embedding of a circuit and
obtaining the proper VLSI layout on the basis of it.
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