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3. 2 Input Encoding Targeting Two-Level Logic . . . . . . . . 27 3.
2. 1 One-Hot Coding and Multiple-Valued Minimization 28 3. 2. 2
Input Constraints and Face Embedding 30 3. 3 Satisfying Encoding
Constraints . . . . . . . 32 3. 3. 1 Definitions . . . . . . . . .
. . . . . . 32 3. 3. 2 Column-Based Constraint Satisfaction 33 3.
3. 3 Row-Based Constraint Satisfaction . . 37 3. 3. 4 Constraint
Satisfaction Using Dichotomies . 38 3. 3. 5 Simulated Annealing for
Constraint Satisfaction 41 3. 4 Input Encoding Targeting Multilevel
Logic. . 43 3. 4. 1 Kernels and Kernel Intersections . . . 44 3. 4.
2 Kernels and Multiple-Valued Variables 46 3. 4. 3 Multiple-Valued
Factorization. . . . . 48 3. 4. 4 Size Estimation in Algebraic
Decomposition . 53 3. 4. 5 The Encoding Step . 54 3. 5 Conclusion .
. . . . . . . . 55 4 Encoding of Symbolic Outputs 57 4. 1 Heuristic
Output Encoding Targeting Two-Level Logic. 59 4. 1. 1 Dominance
Relations. . . . . . . . . . . . . . . . 59 4. 1. 2 Output Encoding
by the Derivation of Dominance Relations . . . . . . . . . . . . .
. . . . . . . . 60 . . 4. 1. 3 Heuristics to Minimize the Number of
Encoding Bits . . . . . . . . . . . . 64 4. 1. 4 Disjunctive
Relationships . . . . . . . . . . . 65 4. 1. 5 Summary . . . . . .
. . . . . . . . . . . . 66 . . 4. 2 Exact Output Encoding Targeting
Two-Level Logic. 66 4. 2. 1 Generation of Generalized Prime
Implicants . 68 4. 2. 2 Selecting a Minimum Encodeable Cover . . .
68 4. 2. 3 Dominance and Disjunctive Relationships to S- isfy
Constraints . . . . . . . . . . . 70 4. 2. 4 Constructing the
Optimized Cover 73 4. 2. 5 Correctness of the Procedure . . 73 4.
2. 6 Multiple Symbolic Outputs . . .
In order to design and build computers that achieve and sustain
high performance, it is essential that reliability issues be
considered care fully. The problem has several aspects. Certainly,
considering reliability implies that an engineer must be able to
analyze how design decisions affect the incidence of failure. For
instance, in order design reliable inte gritted circuits, it is
necessary to analyze how decisions regarding design rules affect
the yield, i.e., the percentage of functional chips obtained by the
manufacturing process. Of equal importance in producing reliable
computers is the detection of failures in its Very Large Scale
Integrated (VLSI) circuit components, caused by errors in the
design specification, implementation, or manufacturing processes.
Design verification involves the checking of the specification of a
design for correctness prior to carrying out an implementation.
Implementation verification ensures that the manual design or
automatic synthesis process is correct, i.e., the mask-level
description correctly implements the specification. Manufacture
test involves the checking of the complex fabrication process for
correctness, i.e., ensuring that there are no manufacturing defects
in the integrated circuit. It should be noted that all the above
verification mechanisms deal not only with verifying the
functionality of the integrated circuit but also its performance."
When it comes to frameworks, the familiar story of the elephant and
the six blind philosophers seems to apply. As each philoso pher
encountered a separate part of the elephant, each pronounced his
considered, but flawed judgement. One blind philosopher felt a leg
and thought it a tree. Another felt the tail and thought he held a
rope. Another felt the elephant's flank and thought he stood before
a wall. We're supposed to learn about snap judgements from this
alle gory, but its author might well have been describing design
automation frameworks. For in the reality of today's product
development requirements, a framework must be many things to many
people. xiv CAD Frameworks: Integration Technology for CAD As the
authors of this book note, framework design is an optimi zation
problem. Somehow, it has to be both a superior rope for one and a
tremendous tree for another. Somehow it needs to provide a standard
environment for exploiting the full potential of computer-aided
engineering tools. And, somehow, it has to make real such
abstractions as interoperability and interchangeability. For years,
we've talked about a framework as something that provides
application-oriented services, just as an operating system provides
system-level support. And for years, that simple statement has hid
the tremendous complexity of actually providing those services.
Our purpose in writing this book was two-fold. First, we wanted to
compile a chronology of the research in the field of mixed-mode
simulation over the last ten to fifteen years. A substantial amount
of work was done during this period of time but most of it was
published in archival form in Masters theses and Ph. D.
dissertations. Since the interest in mixed-mode simulation is
growing, and a thorough review of the state-of-the-art in the area
was not readily available, we thought it appropriate to publish the
information in the form of a book. Secondly, we wanted to provide
enough information to the reader so that a proto type mixed-mode
simulator could be developed using the algorithms in this book. The
SPLICE family of programs is based on the algorithms and techniques
described in this book and so it can also serve as docu mentation
for these programs. ACKNOWLEDGEMENTS The authors would like to
dedicate this book to Prof. D. O. Peder son for inspiring this
research work and for providing many years of support and
encouragement The authors enjoyed many fruitful discus sions and
collaborations with Jim Kleckner, Young Kim, Alberto
Sangiovanni-Vincentelli, and Jacob White, and we thank them for
their contributions. We also thank the countless others who
participated in the research work and read early versions of this
book. Lillian Beck provided many useful suggestions to improve the
manuscript. Yun cheng Ju did the artwork for the illustrations."
Mixed-Mode Simulation and Analog Multilevel Simulation addresses
the problems of simulating entire mixed analog/digital systems in
the time-domain. A complete hierarchy of modeling and simulation
methods for analog and digital circuits is described. Mixed-Mode
Simulation and Analog Multilevel Simulation also provides a
chronology of the research in the field of mixed-mode simulation
and analog multilevel simulation over the last ten to fifteen
years. In addition, it provides enough information to the reader so
that a prototype mixed-mode simulator could be developed using the
algorithms in this book. Mixed-Mode Simulation and Analog
Multilevel Simulation can also be used as documentation for the
SPLICE family of mixed-mode programs as they are based on the
algorithms and techniques described in this book.
Mixed-Mode Simulation and Analog Multilevel Simulation addresses
the problems of simulating entire mixed analog/digital systems in
the time-domain. A complete hierarchy of modeling and simulation
methods for analog and digital circuits is described. Mixed-Mode
Simulation and Analog Multilevel Simulation also provides a
chronology of the research in the field of mixed-mode simulation
and analog multilevel simulation over the last ten to fifteen
years. In addition, it provides enough information to the reader so
that a prototype mixed-mode simulator could be developed using the
algorithms in this book. Mixed-Mode Simulation and Analog
Multilevel Simulation can also be used as documentation for the
SPLICE family of mixed-mode programs as they are based on the
algorithms and techniques described in this book.
When it comes to frameworks, the familiar story of the elephant and
the six blind philosophers seems to apply. As each philoso pher
encountered a separate part of the elephant, each pronounced his
considered, but flawed judgement. One blind philosopher felt a leg
and thought it a tree. Another felt the tail and thought he held a
rope. Another felt the elephant's flank and thought he stood before
a wall. We're supposed to learn about snap judgements from this
alle gory, but its author might well have been describing design
automation frameworks. For in the reality of today's product
development requirements, a framework must be many things to many
people. xiv CAD Frameworks: Integration Technology for CAD As the
authors of this book note, framework design is an optimi zation
problem. Somehow, it has to be both a superior rope for one and a
tremendous tree for another. Somehow it needs to provide a standard
environment for exploiting the full potential of computer-aided
engineering tools. And, somehow, it has to make real such
abstractions as interoperability and interchangeability. For years,
we've talked about a framework as something that provides
application-oriented services, just as an operating system provides
system-level support. And for years, that simple statement has hid
the tremendous complexity of actually providing those services."
In order to design and build computers that achieve and sustain
high performance, it is essential that reliability issues be
considered care fully. The problem has several aspects. Certainly,
considering reliability implies that an engineer must be able to
analyze how design decisions affect the incidence of failure. For
instance, in order design reliable inte gritted circuits, it is
necessary to analyze how decisions regarding design rules affect
the yield, i.e., the percentage of functional chips obtained by the
manufacturing process. Of equal importance in producing reliable
computers is the detection of failures in its Very Large Scale
Integrated (VLSI) circuit components, caused by errors in the
design specification, implementation, or manufacturing processes.
Design verification involves the checking of the specification of a
design for correctness prior to carrying out an implementation.
Implementation verification ensures that the manual design or
automatic synthesis process is correct, i.e., the mask-level
description correctly implements the specification. Manufacture
test involves the checking of the complex fabrication process for
correctness, i.e., ensuring that there are no manufacturing defects
in the integrated circuit. It should be noted that all the above
verification mechanisms deal not only with verifying the
functionality of the integrated circuit but also its performance."
3. 2 Input Encoding Targeting Two-Level Logic . . . . . . . . 27 3.
2. 1 One-Hot Coding and Multiple-Valued Minimization 28 3. 2. 2
Input Constraints and Face Embedding 30 3. 3 Satisfying Encoding
Constraints . . . . . . . 32 3. 3. 1 Definitions . . . . . . . . .
. . . . . . 32 3. 3. 2 Column-Based Constraint Satisfaction 33 3.
3. 3 Row-Based Constraint Satisfaction . . 37 3. 3. 4 Constraint
Satisfaction Using Dichotomies . 38 3. 3. 5 Simulated Annealing for
Constraint Satisfaction 41 3. 4 Input Encoding Targeting Multilevel
Logic. . 43 3. 4. 1 Kernels and Kernel Intersections . . . 44 3. 4.
2 Kernels and Multiple-Valued Variables 46 3. 4. 3 Multiple-Valued
Factorization. . . . . 48 3. 4. 4 Size Estimation in Algebraic
Decomposition . 53 3. 4. 5 The Encoding Step . 54 3. 5 Conclusion .
. . . . . . . . 55 4 Encoding of Symbolic Outputs 57 4. 1 Heuristic
Output Encoding Targeting Two-Level Logic. 59 4. 1. 1 Dominance
Relations. . . . . . . . . . . . . . . . 59 4. 1. 2 Output Encoding
by the Derivation of Dominance Relations . . . . . . . . . . . . .
. . . . . . . . 60 . . 4. 1. 3 Heuristics to Minimize the Number of
Encoding Bits . . . . . . . . . . . . 64 4. 1. 4 Disjunctive
Relationships . . . . . . . . . . . 65 4. 1. 5 Summary . . . . . .
. . . . . . . . . . . . 66 . . 4. 2 Exact Output Encoding Targeting
Two-Level Logic. 66 4. 2. 1 Generation of Generalized Prime
Implicants . 68 4. 2. 2 Selecting a Minimum Encodeable Cover . . .
68 4. 2. 3 Dominance and Disjunctive Relationships to S- isfy
Constraints . . . . . . . . . . . 70 4. 2. 4 Constructing the
Optimized Cover 73 4. 2. 5 Correctness of the Procedure . . 73 4.
2. 6 Multiple Symbolic Outputs . . .
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