System-Level Synthesis deals with the concurrent design of electronic applications, including both hardware and software. The issue has become the bottleneck in the design of electronic systems, including both hardware and software, in several major industrial fields, including telecommunications, automotive and aerospace engineering. The major difficulty with the subject is that it demands contributions from several research fields, including system specification, system architecture, hardware design, and software design. Most existing book cover well only a few aspects of system-level synthesis. The present volume presents a comprehensive discussion of all the aspects of system-level synthesis. Each topic is covered by a contribution written by an international authority on the subject.

Embedded Software for SoC covers all software related aspects of SoC design:
-Embedded and application-domain specific operating systems, interplay between application, operating system, and architecture.
-System architecture for future SoC, application-specific architectures based on embedded processors and requiring sophisticated hardware/software interfaces.
-Compilers and interplay between compilers and architectures.
-Embedded software for applications in the domains of automotive, avionics, multimedia, telecom, networking. Embedded Software for SoC is a must-read for SoC designers that want to broaden their horizons to include the ever-growing embedded software content of their next SoC design. The book will provide embedded software designers invaluable insights into the constraints imposed by the use of embedded software in a SoC context.

Improvement in the quality of integrated circuit designs and a designer's productivity can be achieved by a combination of two factors: Using more structured design methodologies for extensive reuse of existing components and subsystems. It seems that 70% of new designs correspond to existing components that cannot be reused because of a lack of methodologies and tools. Providing higher level design tools allowing to start from a higher level of abstraction. After the success and the widespread acceptance of logic and RTL synthesis, the next step is behavioral synthesis, commonly called architectural or high-level synthesis. Behavioral Synthesis and Component Reuse with VHDL provides methods and techniques for VHDL based behavioral synthesis and component reuse. The goal is to develop VHDL modeling strategies for emerging behavioral synthesis tools. Special attention is given to structured and modular design methods allowing hierarchical behavioral specification and design reuse. The goal of this book is not to discuss behavioral synthesis in general or to discuss a specific tool but to describe the specific issues related to behavioral synthesis of VHDL description. This book targets designers who have to use behavioral synthesis tools or who wish to discover the real possibilities of this emerging technology. The book will also be of interest to teachers and students interested to learn or to teach VHDL based behavioral synthesis.

This title covers all software-related aspects of SoC design, from embedded and application-domain specific operating systems to system architecture for future SoC. It will give embedded software designers invaluable insights into the constraints imposed by the use of embedded software in an SoC context.

Improvement in the quality of integrated circuit designs and a designer's productivity can be achieved by a combination of two factors: * Using more structured design methodologies for extensive reuse of existing components and subsystems. It seems that 70% of new designs correspond to existing components that cannot be reused because of a lack of methodologies and tools. * Providing higher level design tools allowing to start from a higher level of abstraction. After the success and the widespread acceptance of logic and RTL synthesis, the next step is behavioral synthesis, commonly called architectural or high-level synthesis. Behavioral Synthesis and Component Reuse with VHDL provides methods and techniques for VHDL based behavioral synthesis and component reuse. The goal is to develop VHDL modeling strategies for emerging behavioral synthesis tools. Special attention is given to structured and modular design methods allowing hierarchical behavioral specification and design reuse.The goal of this book is not to discuss behavioral synthesis in general or to discuss a specific tool but to describe the specific issues related to behavioral synthesis of VHDL description. This book targets designers who have to use behavioral synthesis tools or who wish to discover the real possibilities of this emerging technology. The book will also be of interest to teachers and students interested to learn or to teach VHDL based behavioral synthesis.

System-Level Synthesis deals with the concurrent design of electronic applications, including both hardware and software. The issue has become the bottleneck in the design of electronic systems, including both hardware and software, in several major industrial fields, including telecommunications, automotive and aerospace engineering. The major difficulty with the subject is that it demands contributions from several research fields, including system specification, system architecture, hardware design, and software design. Most existing book cover well only a few aspects of system-level synthesis. The present volume presents a comprehensive discussion of all the aspects of system-level synthesis. Each topic is covered by a contribution written by an international authority on the subject.