This book presents best selected papers presented at the International Conference on Evolving Technologies for Computing, Communication and Smart World (ETCCS 2020) held on 31 January-1 February 2020 at C-DAC, Noida, India. It is co-organized by Southern Federal University, Russia; University of Jan Wyzykowski (UJW), Polkowice, Poland; and CSI, India. C-DAC, Noida received funding from MietY during the event. The technical services are supported through EasyChair, Turnitin, MailChimp and IAC Education. The book includes current research works in the areas of network and computing technologies, wireless networks and Internet of things (IoT), futuristic computing technologies, communication technologies, security and privacy.

This book presents best selected papers presented at the International Conference on Emerging Trends and Technologies on Intelligent Systems (ETTIS 2021) held from 4 - 5 March 2021 in online mode at C-DAC, Noida, India. The book includes current research works in the areas of artificial intelligence, big data, cyber-physical systems, and security in industrial/real-world settings. The book illustrates on-going research results, projects, surveying works, and industrial experiences that describe significant advances in all of the related areas.

Decoder design consists of choosing the optimal performance circuit style, providing flexibility in configuration of different sizes, sizing of transistors, adding buffers and consideration of fan outs. In this work, high speed reconfigurable decoders of different styles are analyzed for different loads of memory blocks. The power dissipation, delay, frequency & Vdd of various logic styles are analyzed. Evaluation of delay is done by changing Vdd, Speed is improved and power dissipation is minimized by a sizing technique. The memory system plays crucial role in determining optimum performance, power, speed and cost of the simple to complex machines. To improve the access time in memory system, there is requirement of configurable logic block which can be used to select rows and columns of partitioned memory blocks. In a memory for accessing and locating any random data, address decoders are used. The decoder block is contributing in access time and power consumption of memories. In this work, a reconfigurable decoder is proposed to select fewer word lines and to avoid large word line / bit line capacitance.