The more rapid rate of increase in the speed of microprocessor technology than in memory speeds has created a serious 'memory gap' for computer designers and manufacturers. "High Performance Memory Systems" addresses this issue and examines all aspects of improving the memory system performance of general-purpose programs. Current research highlights from both industry and academia focus on: coherence, synchronization, and allocation; power-awareness, reliability, and reconfigurability; software-based memory tuning; architecture design issues; and workload considerations. Topics and features: *both harware and software approaches to scalability and speed disparities are considered *introductory chapter provides broad examination of high performance memory systems *includes coverage of topics from several important international conferences Edited by leading international authorities in the field, this new work provides a survey from researchers and practitioners on advances in technology, architecture, and algorithms that address scalability needs in multiprocessors and the expanding gap between CPU/network and memory speeds. It is ideally suited to researchers and R & D professionals with interests or practice in computer engineering, computer architecture, and processor architecture.

The State of Memory Technology Over the past decade there has been rapid growth in the speed of micropro cessors. CPU speeds are approximately doubling every eighteen months, while main memory speed doubles about every ten years. The International Tech nology Roadmap for Semiconductors (ITRS) study suggests that memory will remain on its current growth path. The ITRS short-and long-term targets indicate continued scaling improvements at about the current rate by 2016. This translates to bit densities increasing at two times every two years until the introduction of 8 gigabit dynamic random access memory (DRAM) chips, after which densities will increase four times every five years. A similar growth pattern is forecast for other high-density chip areas and high-performance logic (e.g., microprocessors and application specific inte grated circuits (ASICs)). In the future, molecular devices, 64 gigabit DRAMs and 28 GHz clock signals are targeted. Although densities continue to grow, we still do not see significant advances that will improve memory speed. These trends have created a problem that has been labeled the Memory Wall or Memory Gap."

This book constitutes the refereed proceedings of the Second International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2007, held in Ghent, Belgium, in January 2007. The 19 revised full papers presented together with one invited keynote paper were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections.

Thisvolumecontainsthesetofpaperspresentedatthe SPECBenchmarkWo- shop 2009 held January 25 in Austin, Texas, USA. The program included eight refereed papers, a keynote talk on virtualization technology benchmarking, an invited paper on power benchmarking and a panel on multi-core benchmarking. EachrefereedpaperwasreviewedbyatleastfourProgramCommitteemembers. The result is a collection of high-quality papers discussing current issues in the area of benchmarking research and technology. A number of people contributed to the success of this workshop.Rudi Eig- mann served as General Chair and ably handled many of the details involved with providing a high-quality meeting. We would like to thank the members of the Program Committee for their time and e?ort in arriving at a high-quality program.We wouldalsolike to acknowledgethe guidance providedby the SPEC Workshop Steering Committee. Wewouldliketothankthesta?atSpringerfortheircooperationandsupport. We want to particularly recognize Dianne Rice for her assistance and guidance, and also Kathy Power, Cathy Sandifer and the whole SPEC o?ce for their help. And ?nally, we want to thank all SPEC members for their continued support and sponsorship of this meeting. January 2009 David Kaeli Kai Sachs Organization SPEC Benchmark Workshop 2009 was sponsored by the Standard Performance EvaluationCorporationincooperationwithIEEETechnicalCommitteeonC- puter Architecture (TCAA)