Multithreaded computer architecture has emerged as one of the most promising and exciting avenues for the exploitation of parallelism. This new field represents the confluence of several independent research directions which have united over a common set of issues and techniques. Multithreading draws on recent advances in dataflow, RISC, compiling for fine-grained parallel execution, and dynamic resource management. It offers the hope of dramatic performance increases through parallel execution for a broad spectrum of significant applications based on extensions to traditional' approaches. Multithreaded Computer Architecture is divided into four parts, reflecting four major perspectives on the topic. Part I provides the reader with basic background information, definitions, and surveys of work which have in one way or another been pivotal in defining and shaping multithreading as an architectural discipline. Part II examines key elements of multithreading, highlighting the fundamental nature of latency and synchronization. This section presents clever techniques for hiding latency and supporting large synchronization name spaces. Part III looks at three major multithreaded systems, considering issues of machine organization and compilation strategy. Part IV concludes the volume with an analysis of multithreaded architectures, showcasing methodologies and actual measurements. Multithreaded Computer Architecture: A Summary of the State of the Art is an excellent reference source and may be used as a text for advanced courses on the subject.

This monograph evolved from my Ph. D dissertation completed at the Laboratory of Computer Science, MIT, during the Summer of 1986. In my dissertation I proposed a pipelined code mapping scheme for array operations on static dataflow architectures. The main addition to this work is found in Chapter 12, reflecting new research results developed during the last three years since I joined McGill University-results based upon the principles in my dissertation. The terminology dataflow soft ware pipelining has been consistently used since publication of our 1988 paper on the argument-fetching dataflow architecture model at McGill University 43]. In the first part of this book we describe the static data flow graph model as an operational model for concurrent computation. We look at timing considerations for program graph execution on an ideal static dataflow computer, examine the notion of pipe lining, and characterize its performance. We discuss balancing techniques used to transform certain graphs into fully pipelined data flow graphs. In particular, we show how optimal balancing of an acyclic data flow graph can be formulated as a linear programming problem for which an optimal solution exists. As a major result, we show the optimal balancing problem of acyclic data flow graphs is reduceable to a class of linear programming problem, the net work flow problem, for which well-known efficient algorithms exist. This result disproves the conjecture that such problems are computationally hard."

During a meeting in Toronto last winter, Mike Jenkins, Bob Bernecky and I were discussing how the two existing theories on arrays influenced or were in fluenced by programming languages and systems. More's Army Theory was the basis for NIAL and APL2 and Mullin's A Mathematics of A rmys(MOA), is being used as an algebra of arrays in functional and A-calculus based pro gramming languages. MOA was influenced by Iverson's initial and extended algebra, the foundations for APL and J respectively. We discussed that there is a lot of interest in the Computer Science and Engineering communities concerning formal methods for languages that could support massively parallel operations in scientific computing, a back to-roots interest for both Mike and myself. Languages for this domain can no longer be informally developed since it is necessary to map languages easily to many multiprocessor architectures. Software systems intended for parallel computation require a formal basis so that modifications can be done with relative ease while ensuring integrity in design. List based lan guages are profiting from theoretical foundations such as the Bird-Meertens formalism. Their theory has been successfully used to describe list based parallel algorithms across many classes of architectures."

The ever decreasing price/performance ratio of microcontrollers makes it economically attractive to replace more and more conventional mechanical or electronic control systems within many products by embedded real-time computer systems. An embedded real-time computer system is always part of a well-specified larger system, which we call an intelligent product. Although most intelligent products start out as stand-alone units, many of them are required to interact with other systems at a later stage. At present, many industries are in the middle of this transition from stand-alone products to networked embedded systems. This transition requires reflection and architecting: the complexity of the evolving distributed artifact can only be controlled if careful planning and principled design methods replace the ad-hoc engineering of the first version of many standalone embedded products.Design Methods and Applications for Distributed Embedded Systems documents recent approaches and results presented at the IFIP TC10 Working Conference on Distributed and Parallel Embedded Systems (DIPES 2004), which was held in August 2004 as a co-located conference of the 18th IFIP World Computer Congress in Toulouse, France, and sponsored by the International Federation for Information Processing (IFIP). The topics which have been chosen for this working conference are very timely: model-based design methods, design space exploration, design methodologies and user interfaces, networks and communication, scheduling and resource management, fault detection and fault tolerance, and verification and analysis. These topics are supplemented by several hardware and application oriented papers.

This monograph evolved from my Ph. D dissertation completed at the Laboratory of Computer Science, MIT, during the Summer of 1986. In my dissertation I proposed a pipelined code mapping scheme for array operations on static dataflow architectures. The main addition to this work is found in Chapter 12, reflecting new research results developed during the last three years since I joined McGill University-results based upon the principles in my dissertation. The terminology dataflow soft ware pipelining has been consistently used since publication of our 1988 paper on the argument-fetching dataflow architecture model at McGill University 43]. In the first part of this book we describe the static data flow graph model as an operational model for concurrent computation. We look at timing considerations for program graph execution on an ideal static dataflow computer, examine the notion of pipe lining, and characterize its performance. We discuss balancing techniques used to transform certain graphs into fully pipelined data flow graphs. In particular, we show how optimal balancing of an acyclic data flow graph can be formulated as a linear programming problem for which an optimal solution exists. As a major result, we show the optimal balancing problem of acyclic data flow graphs is reduceable to a class of linear programming problem, the net work flow problem, for which well-known efficient algorithms exist. This result disproves the conjecture that such problems are computationally hard."

Multithreaded computer architecture has emerged as one of the most promising and exciting avenues for the exploitation of parallelism. This new field represents the confluence of several independent research directions which have united over a common set of issues and techniques. Multithreading draws on recent advances in dataflow, RISC, compiling for fine-grained parallel execution, and dynamic resource management. It offers the hope of dramatic performance increases through parallel execution for a broad spectrum of significant applications based on extensions to `traditional' approaches. Multithreaded Computer Architecture is divided into four parts, reflecting four major perspectives on the topic. Part I provides the reader with basic background information, definitions, and surveys of work which have in one way or another been pivotal in defining and shaping multithreading as an architectural discipline. Part II examines key elements of multithreading, highlighting the fundamental nature of latency and synchronization. This section presents clever techniques for hiding latency and supporting large synchronization name spaces. Part III looks at three major multithreaded systems, considering issues of machine organization and compilation strategy. Part IV concludes the volume with an analysis of multithreaded architectures, showcasing methodologies and actual measurements. Multithreaded Computer Architecture: A Summary of the State of the Art is an excellent reference source and may be used as a text for advanced courses on the subject.

During a meeting in Toronto last winter, Mike Jenkins, Bob Bernecky and I were discussing how the two existing theories on arrays influenced or were in fluenced by programming languages and systems. More's Army Theory was the basis for NIAL and APL2 and Mullin's A Mathematics of A rmys(MOA), is being used as an algebra of arrays in functional and A-calculus based pro gramming languages. MOA was influenced by Iverson's initial and extended algebra, the foundations for APL and J respectively. We discussed that there is a lot of interest in the Computer Science and Engineering communities concerning formal methods for languages that could support massively parallel operations in scientific computing, a back to-roots interest for both Mike and myself. Languages for this domain can no longer be informally developed since it is necessary to map languages easily to many multiprocessor architectures. Software systems intended for parallel computation require a formal basis so that modifications can be done with relative ease while ensuring integrity in design. List based lan guages are profiting from theoretical foundations such as the Bird-Meertens formalism. Their theory has been successfully used to describe list based parallel algorithms across many classes of architectures."

The Third International Workshop on OpenMP, IWOMP 2007, was held at Beijing, China.This year'sworkshopcontinuedits traditionofbeingthe premier opportunity to learn more about OpenMP, to obtain practical experience and to interact with OpenMP users and developers. The workshop also served as a forum for presenting insights gained by practical experience, as well as research ideas and results related to OpenMP. A total of 28 submissions were received in response to a call for papers. Each submissionwasevaluatedbythreereviewersandadditionalreviewswerereceived for some papers. Based on the feedback received, 22 papers were accepted for inclusion in the proceedings. Of the 22 papers, 14 were accepted as full papers. We also accepted eight short papers, for each of which there was an opportunity to givea shortpresentationat the workshop, followed byposter demonstrations. Each paper was judged according to its originality, innovation, readability, and relevance to the expected audience. Due to the limited scope and time of the workshop and the high number of submissions received, only 50% of the total submissions were able to be included in the ?nal program. In addition to the contributed papers, the IWOMP 2007 program featured several keynote and banquet speakers: Trevor Mudge, Randy Brown, and Shah, Sanjiv. These speakers were selected due to their signi?cant contributions and reputation in the ?eld. A tutorial session and labs were also associated with IWOMP 2007.

Welcome to the proceedings of the 2004 International Conference on Embedded and Ubiquitous Computing (EUC 2004) which was held in Aizu-Wakamatsu City, Japan, 25-27 August 2004. Embedded and ubiquitous computing are emerging rapidly as exciting new paradigms and disciplines to provide computing and communication services all the time, everywhere. Its systems are now invading every aspect of life to the point that they are disappearing inside all sorts of appliances or can be worn unobtrusively as part of clothing and jewelry, etc. This emergence is a natural outcome of research and technological advances in embedded systems, pervasive computing and communications, wireless networks, mobile computing, distri- ted computing and agent technologies, etc. Its explosive impact on academia, industry, government and daily life can be compared to that of electric motors over the past century but promises to revolutionize life much more profoundly than elevators, electric motors or even personal computer evolution ever did. The EUC 2004 conference provided a forum for engineers and scientists in academia, industry, and government to address all the resulting profound ch- lenges including technical, safety, social, legal, political, and economic issues, and to present and discuss their ideas, results, work in progress and experience on all aspects of embedded and ubiquitous computing. There was a very large number of paper submissions (260) from more than 20countriesandregions, includingnotonlyAsiaandthePaci?c, butalsoEurope and North America. All submissions were reviewed by at least three program or technical committee members or external reviewer

This book constitutes the proceedings of the 13th IFIP WG 10.3International Conference on Network and Parallel Computing, NPC 2016,held in Xi'an, China, in October 2016. The 17 full papers presented were carefully reviewed and selected from 99 submissions. They are organized in the following topical sections; memory: non-volatile, solid state drives, hybrid systems; resilience and reliability; scheduling and load-balancing; heterogeneous systems; data processing and big data; and algorithms and computational models.