This book addresses Software-Defined Radio (SDR) baseband processing from the computer architecture point of view, providing a detailed exploration of different computing platforms by classifying different approaches, highlighting the common features related to SDR requirements and by showing pros and cons of the proposed solutions. It covers architectures exploiting parallelism by extending single-processor environment (such as VLIW, SIMD, TTA approaches), multi-core platforms distributing the computation to either a homogeneous array or a set of specialized heterogeneous processors, and architectures exploiting fine-grained, coarse-grained, or hybrid reconfigurability.

This book provides an overview of positioning technologies, applications and services in a format accessible to a wide variety of readers. Readers who have always wanted to understand how satellite-based positioning, wireless network positioning, inertial navigation, and their combinations work will find great value in this book. Readers will also learn about the advantages and disadvantages of different positioning methods, their limitations and challenges. Cognitive positioning, adding the brain to determine which technologies to use at device runtime, is introduced as well. Coverage also includes the use of position information for Location Based Services (LBS), as well as context-aware positioning services, designed for better user experience.

This book provides an overview of positioning technologies, applications and services in a format accessible to a wide variety of readers. Readers who have always wanted to understand how satellite-based positioning, wireless network positioning, inertial navigation, and their combinations work will find great value in this book. Readers will also learn about the advantages and disadvantages of different positioning methods, their limitations and challenges. Cognitive positioning, adding the brain to determine which technologies to use at device runtime, is introduced as well. Coverage also includes the use of position information for Location Based Services (LBS), as well as context-aware positioning services, designed for better user experience.

This book covers multi-band Galileo receivers (especially E1-E5 bands of Galileo) and addresses all receiver building blocks, from the antenna and front end, through details of the baseband receiver processing blocks, up to the navigation processing, including the Galileo message structure and Position, Velocity, Time (PVT) computation. Moreover, hybridization solutions with communications systems for improved localization are discussed and an open-source GNSS receiver platform (available for download) developed at Tampere University of Technology (TUT) is addressed in detail.

This book covers multi-band Galileo receivers (especially E1-E5 bands of Galileo) and addresses all receiver building blocks, from the antenna and front end, through details of the baseband receiver processing blocks, up to the navigation processing, including the Galileo message structure and Position, Velocity, Time (PVT) computation. Moreover, hybridization solutions with communications systems for improved localization are discussed and an open-source GNSS receiver platform (available for download) developed at Tampere University of Technology (TUT) is addressed in detail.

Here is an extremely useful book that provides insight into a number of different flavors of processor architectures and their design, software tool generation, implementation, and verification. After a brief introduction to processor architectures and how processor designers have sometimes failed to deliver what was expected, the authors introduce a generic flow for embedded on-chip processor design and start to explore the vast design space of on-chip processing. The authors cover a number of different types of processor core.

In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design.
Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design.
The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.

Processor Design provides insight into a number of different flavors of processor architectures and their design, software tool generation, implementation, and verification. After a brief introduction to processor architectures and how processor designers have sometimes failed to deliver what was expected, the authors introduce a generic flow for embedded on-chip processor design and start to explore the vast design space of on-chip processing. The types of processor cores covered include general purpose RISC cores, traditional DSP, a VLIW approach to signal processing, processor cores that can be customized for specific applications, reconfigurable processors, protocol processors, Java engines, and stream processors. Co-processor and multi-core design approaches that deliver application-specific performance over and above that which is available from single-core designs are also described.

In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design.
Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design.
The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.

This book addresses Software-Defined Radio (SDR) baseband processing from the computer architecture point of view, providing a detailed exploration of different computing platforms by classifying different approaches, highlighting the common features related to SDR requirements and by showing pros and cons of the proposed solutions. It covers architectures exploiting parallelism by extending single-processor environment (such as VLIW, SIMD, TTA approaches), multi-core platforms distributing the computation to either a homogeneous array or a set of specialized heterogeneous processors, and architectures exploiting fine-grained, coarse-grained, or hybrid reconfigurability.