Internet-of-Things (IoT) can be envisaged as a dynamic network of interconnected physical and virtual entities ("things"), with their own identities and attributes, seamlessly integrated in order to e.g. actively participate in economic or societal processes, interact with services, and react autonomously to events while sensing the environment. By enabling things to connect and becoming recognizable, while providing them with intelligence, informed and context based decisions are expected in a broad range of domains spanning from health and elderly care to energy efficiency, either providing business competitive advantages to companies, either addressing key social concerns. The level of connectivity and analytical intelligence provided by the IoT paradigm is expected to allow creating new services that would not be feasible by other means. This CAS4IoT book targets post-graduate students and design engineers, with the skills to understand and design a broader range of analog, digital and mixed-signal circuits and systems, in the field of IoT, spanning from data converters for sensor interfaces to radios, ensuring a good balance between academia and industry, combined with a judicious selection of worldwide distinguished authors.

This book is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. This implementation is demonstrated by the presentation of several circuits where the MOS parametric amplifier cell is used: small gain amplifier, comparator with embedded pre-amplification, discrete-time mixer/IIR-Filter, and analog-to-digital converter (ADC). Experimental results are shown to validate the overall design technique.

This book shows that digitally assisted analog to digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits.

This book is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. This implementation is demonstrated by the presentation of several circuits where the MOS parametric amplifier cell is used: small gain amplifier, comparator with embedded pre-amplification, discrete-time mixer/IIR-Filter, and analog-to-digital converter (ADC). Experimental results are shown to validate the overall design technique.

Systematic Design for Optimisation of Pipelined ADCs proposes and develops new strategies, methodologies and tools for designing low-power and low-area CMOS pipelined A/D converters. The task is tackled by following a scientifically-consistent approach. First of all, the state of the art in pipeline A/D converters is analysed with a double purpose: a) to identify the best suited among different strategies reported in literature and taking into account the objectives pursued; b) to identify the drawbacks of these strategies as a basic first step to improve them. Then, the book proposes a top-down design approach for implementing high-performance low-power and low-area CMOS pipelined A/D converters through: The conception, development and implementation of self-calibrated techniques to extend the linearity of some critical stages in the architecture of pipelined ADCs. The detailed analysis and modelling of some major non-idealities that limit the physical realisation of pipelined ADCs and the proposal, development and implementation of design methodologies to support systematic design of optimised instances of these converters which combine maximum performance with minimum power dissipation and minimum area occupation. /LIST Several implementations together with consistent measured results are presented. In particular, a practical realisation of a low-power 14-bit 5MS/s CMOS pipelined ADC with background analogue self-calibration is fully described. The proposed approach is fully in line with the best practice regarding the design of mixed-signal integrated circuits. On the one hand, drawbacks of currently existing solutions are overcame through innovative strategies and, on the other hand, the expert knowledge is packaged and made available for re-usability by the community of circuit designers. Finally, feasibility of the strategies and the associated encapsulated knowledge is granted through experimental validation of working silicon. Systematic Design for Optimisation of Pipelined ADCs serves as an excellent reference for analogue design engineers especially designers of low-power CMOS A/D converters. The book may also be used as a text for advanced reading on the subject."

Low Power UWB CMOS Radar Sensors deals with the problem of designing low cost CMOS radar sensors. The radar sensor uses UWB signals in order to obtain a reasonable target separation capability, while maintaining a maximum signal frequency below 2 GHz. This maximum frequency value is well within the reach of current CMOS technologies. The use of UWB signals means that most of the methodologies used in the design of circuits and systems that process narrow band signals, can no longer be applied.

Low Power UWB CMOS Radar Sensors provides an analysis between the interaction of UWB signals, the antennas and the processing circuits. This analysis leads to some interesting conclusions on the types of antennas and types of circuits that should be used. A methodology to compare the noise performance of UWB processing circuits is also derived. This methodology is used to analyze and design the constituting circuits of the radar transceiver. In order to validate the design methodology a CMOS prototype is designed and experimentally evaluated.

Low Power UWB CMOS Radar Sensors deals with the problem of designing low cost CMOS radar sensors. The radar sensor uses UWB signals in order to obtain a reasonable target separation capability, while maintaining a maximum signal frequency below 2 GHz. This maximum frequency value is well within the reach of current CMOS technologies. The use of UWB signals means that most of the methodologies used in the design of circuits and systems that process narrow band signals, can no longer be applied.

Low Power UWB CMOS Radar Sensors provides an analysis between the interaction of UWB signals, the antennas and the processing circuits. This analysis leads to some interesting conclusions on the types of antennas and types of circuits that should be used. A methodology to compare the noise performance of UWB processing circuits is also derived. This methodology is used to analyze and design the constituting circuits of the radar transceiver. In order to validate the design methodology a CMOS prototype is designed and experimentally evaluated.

This excellent reference proposes and develops new strategies, methodologies and tools for designing low-power and low-area CMOS pipelined A/D converters. The task is tackled by following a scientifically-consistent approach. The book may also be used as a text for advanced reading on the subject.

This book addresses the task of circuit sizing optimization. A novel framework is introduced, based on time-domain analysis, genetic algorithm optimization, and distributed processing. The time-domain optimization methodology is based on the step response of the amplifier, which simplifies the circuit evaluation and helps the optimization process to converge faster. Complex and accurate device models (e.g. BSIM3v3) are integrated. The time-domain evaluation of the amplifier is used by the genetic algorithm optimization kernel, in the classification of the genetic individuals. Distributed processing is also employed to address the increasing processing time demanded by the complex circuit analysis, and the accurate models of the circuit devices. Platform assessment is carried by several examples, which have been optimized and successfully used, embedded, in larger systems, such as data converters. A dedicated example of an inverter-based self-biased two-stage amplifier has been designed, laid-out, fabricated, and experimentally evaluated. The measured results are a direct demonstration of the effectiveness of the proposed time-domain optimization methodology.