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Boundary-Scan Interconnect Diagnosis (Paperback, Softcover reprint of the original 1st ed. 2001): Jose T De Sousa, Peter Y.K.... Boundary-Scan Interconnect Diagnosis (Paperback, Softcover reprint of the original 1st ed. 2001)
Jose T De Sousa, Peter Y.K. Cheung
R4,526 Discovery Miles 45 260 Ships in 10 - 15 working days

Boundary-Scan Interconnect Diagnosis explains how to synthesize digital diagnostic sequences for wire interconnects using boundary-scan, and how to assess the quality of those sequences. Its importance has to do with designing complex electronic systems using pre-designed intellectual property (IP) cores, which is becoming increasingly popular nowadays. Since tests for pre-designed cores can be supplied with the cores themselves, the only additional tests that need to be developed to test and diagnose the entire system are those for wire interconnects between the cores. Besides the trivial solutions that are often used to solve this problem, there are many more methods that enable significant optimizations of test vector length and/or diagnostic resolution. The book surveys all existing methods of this kind and proposes new ones. In the new approach circuit and interconnect faults are carefully modeled, and graph techniques are applied to solve the problem. The original feature of the new method is the fact that it can be adjusted to provide shorter test sequences and/or greater diagnostic resolution. The effectiveness of existing and proposed methods is then evaluated using real electronic assemblies and published statistical data for an actual manufacturing process from HP.

Boundary-Scan Interconnect Diagnosis (Hardcover, 2001 ed.): Jose T De Sousa, Peter Y.K. Cheung Boundary-Scan Interconnect Diagnosis (Hardcover, 2001 ed.)
Jose T De Sousa, Peter Y.K. Cheung
R4,673 Discovery Miles 46 730 Ships in 10 - 15 working days

This pioneering text explains how to synthesize digital diagnostic sequences for wire interconnects using boundary-scan, and how to assess the quality of those sequences. It takes a new approach, carefully modelling circuit and interconnect faults, and applying graph techniques to solve problems.

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