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Engineering productivity in integrated circuit product design and -
velopment today is limited largely by the effectiveness of the CAD
tools used. For those domains of product design that are highly
dependent on transistor-level circuit design and optimization, such
as high-speed logic and memory, mixed-signal analog-digital int-
faces, RF functions, power integrated circuits, and so forth,
circuit simulation is perhaps the single most important tool. As
the complexity and performance of integrated electronic systems has
increased with scaling of technology feature size, the capabilities
and sophistication of the underlying circuit simulation tools have
correspondingly increased. The absolute size of circuits requiring
transistor-level simulation has increased dramatically, creating
not only problems of computing power resources but also problems of
task organization, complexity management, output representation,
initial condition setup, and so forth. Also, as circuits of more c-
plexity and mixed types of functionality are attacked with simu-
tion, the spread between time constants or event time scales within
the circuit has tended to become wider, requiring new strategies in
simulators to deal with large time constant spreads.
The Verilog Hardware Description Language (Verilog-HDL) has long
been the most popular language for describing complex digital
hardware. It started life as a prop- etary language but was donated
by Cadence Design Systems to the design community to serve as the
basis of an open standard. That standard was formalized in 1995 by
the IEEE in standard 1364-1995. About that same time a group named
Analog Verilog International formed with the intent of proposing
extensions to Verilog to support analog and mixed-signal
simulation. The first fruits of the labor of that group became
available in 1996 when the language definition of Verilog-A was
released. Verilog-A was not intended to work directly with
Verilog-HDL. Rather it was a language with Similar syntax and
related semantics that was intended to model analog systems and be
compatible with SPICE-class circuit simulation engines. The first
implementation of Verilog-A soon followed: a version from Cadence
that ran on their Spectre circuit simulator. As more
implementations of Verilog-A became available, the group defining
the a- log and mixed-signal extensions to Verilog continued their
work, releasing the defi- tion of Verilog-AMS in 2000. Verilog-AMS
combines both Verilog-HDL and Verilog-A, and adds additional
mixed-signal constructs, providing a hardware description language
suitable for analog, digital, and mixed-signal systems. Again,
Cadence was first to release an implementation of this new
language, in a product named AMS Designer that combines their
Verilog and Spectre simulation engines.
Engineering productivity in integrated circuit product design and -
velopment today is limited largely by the effectiveness of the CAD
tools used. For those domains of product design that are highly
dependent on transistor-level circuit design and optimization, such
as high-speed logic and memory, mixed-signal analog-digital int-
faces, RF functions, power integrated circuits, and so forth,
circuit simulation is perhaps the single most important tool. As
the complexity and performance of integrated electronic systems has
increased with scaling of technology feature size, the capabilities
and sophistication of the underlying circuit simulation tools have
correspondingly increased. The absolute size of circuits requiring
transistor-level simulation has increased dramatically, creating
not only problems of computing power resources but also problems of
task organization, complexity management, output representation,
initial condition setup, and so forth. Also, as circuits of more c-
plexity and mixed types of functionality are attacked with simu-
tion, the spread between time constants or event time scales within
the circuit has tended to become wider, requiring new strategies in
simulators to deal with large time constant spreads.
The Verilog Hardware Description Language (Verilog-HDL) has long
been the most popular language for describing complex digital
hardware. It started life as a prop- etary language but was donated
by Cadence Design Systems to the design community to serve as the
basis of an open standard. That standard was formalized in 1995 by
the IEEE in standard 1364-1995. About that same time a group named
Analog Verilog International formed with the intent of proposing
extensions to Verilog to support analog and mixed-signal
simulation. The first fruits of the labor of that group became
available in 1996 when the language definition of Verilog-A was
released. Verilog-A was not intended to work directly with
Verilog-HDL. Rather it was a language with Similar syntax and
related semantics that was intended to model analog systems and be
compatible with SPICE-class circuit simulation engines. The first
implementation of Verilog-A soon followed: a version from Cadence
that ran on their Spectre circuit simulator. As more
implementations of Verilog-A became available, the group defining
the a- log and mixed-signal extensions to Verilog continued their
work, releasing the defi- tion of Verilog-AMS in 2000. Verilog-AMS
combines both Verilog-HDL and Verilog-A, and adds additional
mixed-signal constructs, providing a hardware description language
suitable for analog, digital, and mixed-signal systems. Again,
Cadence was first to release an implementation of this new
language, in a product named AMS Designer that combines their
Verilog and Spectre simulation engines.
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