This book focuses on the acceleration of emerging irregular sparse workloads, posed by novel artificial intelligent (AI) models and sparse linear algebra. Specifically, the book outlines several co-optimized hardware-software solutions for a highly promising class of emerging sparse AI models called Probabilistic Circuit (PC) and a similar sparse matrix workload for triangular linear systems (SpTRSV). The authors describe optimizations for the entire stack, targeting applications, compilation, hardware architecture and silicon implementation, resulting in orders of magnitude higher performance and energy-efficiency compared to the existing state-of-the-art solutions. Thus, this book provides important building blocks for the upcoming generation of edge AI platforms.

This book discusses the design and implementation aspects of ultra-low power biosignal acquisition platforms that exploit analog-assisted and algorithmic approaches for power savings.The authors describe an approach referred to as "analog-and-algorithm-assisted" signal processing.This enables significant power consumption reductions by implementing low power biosignal acquisition systems, leveraging analog preprocessing and algorithmic approaches to reduce the data rate very early in the signal processing chain.They demonstrate savings for wearable sensor networks (WSN) and body area networks (BAN), in the sensors' stimulation power consumption, as well in the power consumption of the digital signal processing and the radio link. Two specific implementations, an adaptive sampling electrocardiogram (ECG) acquisition and a compressive sampling (CS) photoplethysmogram (PPG) acquisition system, are demonstrated. First book to present the so called, "analog-and-algorithm-assisted" approaches for ultra-low power biosignal acquisition and processing platforms; Covers the recent trend of "beyond Nyquist rate" signal acquisition and processing in detail, including adaptive sampling and compressive sampling paradigms; Includes chapters on compressed domain feature extraction, as well as acquisition of photoplethysmogram, an emerging optical sensing modality, including compressive sampling based PPG readout with embedded feature extraction; Discusses emerging trends in sensor fusion for improving the signal integrity, as well as lowering the power consumption of biosignal acquisition systems.

Smart energy management, both at design time and at run time, is indispensable in modern radios. It requires a careful trade-off between the system s performance, and its power consumption. Moreover, the design has to be dynamically reconfigurable to optimally balance these parameters at run time, depending on the current operating conditions.

Energy Scalable Radio Design describes and applies an energy-driven design strategy to the design of an energy-efficient, highly scalable, pulsed UWB receiver, suitable for low data rate communication and sub-cm ranging. This book meticulously covers the different design steps and the adopted optimizations: System level air interface selection, architectural/algorithmic design space exploration, algorithmic refinement (acquisition, synchronization and ranging algorithms) and circuit level (RTL) implementation based on the FLEXmodule-concept. Measurement results demonstrate the effectiveness and necessity of the energy-driven design strategy."

This book explores and motivates the need for building homogeneous and heterogeneous multi-core systems for machine learning to enable flexibility and energy-efficiency. Coverage focuses on a key aspect of the challenges of (extreme-)edge-computing, i.e., design of energy-efficient and flexible hardware architectures, and hardware-software co-optimization strategies to enable early design space exploration of hardware architectures. The authors investigate possible design solutions for building single-core specialized hardware accelerators for machine learning and motivates the need for building homogeneous and heterogeneous multi-core systems to enable flexibility and energy-efficiency. The advantages of scaling to heterogeneous multi-core systems are shown through the implementation of multiple test chips and architectural optimizations.

This book proposes probabilistic machine learning models that represent the hardware properties of the device hosting them. These models can be used to evaluate the impact that a specific device configuration may have on resource consumption and performance of the machine learning task, with the overarching goal of balancing the two optimally. The book first motivates extreme-edge computing in the context of the Internet of Things (IoT) paradigm. Then, it briefly reviews the steps involved in the execution of a machine learning task and identifies the implications associated with implementing this type of workload in resource-constrained devices. The core of this book focuses on augmenting and exploiting the properties of Bayesian Networks and Probabilistic Circuits in order to endow them with hardware-awareness. The proposed models can encode the properties of various device sub-systems that are typically not considered by other resource-aware strategies, bringing about resource-saving opportunities that traditional approaches fail to uncover. The performance of the proposed models and strategies is empirically evaluated for several use cases. All of the considered examples show the potential of attaining significant resource-saving opportunities with minimal accuracy losses at application time. Overall, this book constitutes a novel approach to hardware-algorithm co-optimization that further bridges the fields of Machine Learning and Electrical Engineering.

This book covers algorithmic and hardware implementation techniques to enable embedded deep learning. The authors describe synergetic design approaches on the application-, algorithmic-, computer architecture-, and circuit-level that will help in achieving the goal of reducing the computational cost of deep learning algorithms. The impact of these techniques is displayed in four silicon prototypes for embedded deep learning. Gives a wide overview of a series of effective solutions for energy-efficient neural networks on battery constrained wearable devices; Discusses the optimization of neural networks for embedded deployment on all levels of the design hierarchy - applications, algorithms, hardware architectures, and circuits - supported by real silicon prototypes; Elaborates on how to design efficient Convolutional Neural Network processors, exploiting parallelism and data-reuse, sparse operations, and low-precision computations; Supports the introduced theory and design concepts by four real silicon prototypes. The physical realization's implementation and achieved performances are discussed elaborately to illustrated and highlight the introduced cross-layer design concepts.

Smart energy management, both at design time and at run time, is indispensable in modern radios. It requires a careful trade-off between the system s performance, and its power consumption. Moreover, the design has to be dynamically reconfigurable to optimally balance these parameters at run time, depending on the current operating conditions.

Energy Scalable Radio Design describes and applies an energy-driven design strategy to the design of an energy-efficient, highly scalable, pulsed UWB receiver, suitable for low data rate communication and sub-cm ranging. This book meticulously covers the different design steps and the adopted optimizations: System level air interface selection, architectural/algorithmic design space exploration, algorithmic refinement (acquisition, synchronization and ranging algorithms) and circuit level (RTL) implementation based on the FLEXmodule-concept. Measurement results demonstrate the effectiveness and necessity of the energy-driven design strategy."

This book proposes probabilistic machine learning models that represent the hardware properties of the device hosting them. These models can be used to evaluate the impact that a specific device configuration may have on resource consumption and performance of the machine learning task, with the overarching goal of balancing the two optimally. The book first motivates extreme-edge computing in the context of the Internet of Things (IoT) paradigm. Then, it briefly reviews the steps involved in the execution of a machine learning task and identifies the implications associated with implementing this type of workload in resource-constrained devices. The core of this book focuses on augmenting and exploiting the properties of Bayesian Networks and Probabilistic Circuits in order to endow them with hardware-awareness. The proposed models can encode the properties of various device sub-systems that are typically not considered by other resource-aware strategies, bringing about resource-saving opportunities that traditional approaches fail to uncover. The performance of the proposed models and strategies is empirically evaluated for several use cases. All of the considered examples show the potential of attaining significant resource-saving opportunities with minimal accuracy losses at application time. Overall, this book constitutes a novel approach to hardware-algorithm co-optimization that further bridges the fields of Machine Learning and Electrical Engineering.

This book covers algorithmic and hardware implementation techniques to enable embedded deep learning. The authors describe synergetic design approaches on the application-, algorithmic-, computer architecture-, and circuit-level that will help in achieving the goal of reducing the computational cost of deep learning algorithms. The impact of these techniques is displayed in four silicon prototypes for embedded deep learning. Gives a wide overview of a series of effective solutions for energy-efficient neural networks on battery constrained wearable devices; Discusses the optimization of neural networks for embedded deployment on all levels of the design hierarchy - applications, algorithms, hardware architectures, and circuits - supported by real silicon prototypes; Elaborates on how to design efficient Convolutional Neural Network processors, exploiting parallelism and data-reuse, sparse operations, and low-precision computations; Supports the introduced theory and design concepts by four real silicon prototypes. The physical realization's implementation and achieved performances are discussed elaborately to illustrated and highlight the introduced cross-layer design concepts.