Yield and reliability of memories have degraded with device and voltage scaling in the nano-scale era, due to ever-increasing hard/soft errors and device parameter variations. This book systematically describes these yield and reliability issues in terms of mathematics and engineering, as well as an array of repair techniques, based on the authors' long careers in developing memories and low-voltage CMOS circuits. Nanoscale Memory Repair gives a detailed explanation of the various yield models and calculations, as well as various, practical logic and circuits that are critical for higher yield and reliability.

Ultra-low voltage large-scale integrated circuits (LSIs) in nano-scale technologies are needed to:

-Meet the needs of a rapidly growing mobile cell phone market
-Offset a significant increase in the power dissipation of high-end microprocessor units.

Low power large capacity memories are a necessary component of low voltage LSIs. Many challenges arise in the process of achieving such memories as their devices and voltages are scaled down below 100nm and sub-1-V. A high signal-to-noise (S/N) ratio design is necessary to deal with small signal voltages from low-voltage memory cells in the presence of large noise sources in a high-density memory-cell array. Moreover, innovative circuits and devices are needed to resolve the increasing problems of leakage currents and variability in both speed and leakage. Since the solutions to these problems lie between different fields, (e.g., digital and analog, SRAM and DRAM) a multidisciplinary approach is needed.

Ultra-Low Voltage Nano-Scale Memories is an authoritative monograph that addresses these challenges. This book is written for memory and circuit designers as well as for researchers and students who are interested in ultra-low voltage nano-scale memory LSIs.

The goal of Ultra-Low Voltage Nano-Scale Memories is to provide a detailed explanation of the state-of-the-art nanometer and sub-1-V memory LSIs that are playing decisive roles in power conscious systems. Emerging problems between the device, circuit, and system levels are systematically discussed in terms of reliable high-speed operations of memory cells and peripheral logic circuits. The effectiveness of solutions at device and circuit levels is also described at length. Voltage scaling is prevented by many resulting problems, such as the ever-decreasing signal-to-noise-ratio and voltage margin of many tiny flip-flop circuits in a memory-cell array and peripheral circuits, and the ever-increasing leakage and variation in speed caused by variations in process, voltage, and temperature. The problems and promising solutions at device and circuit levels are discussed in detail through clarifying noise components in an array, and even essential differences in ultra-low voltage operations between DRAMs and SRAMs. Moreover, various kinds of on-chip voltage converters necessary to solve the problems with internal power-supply managements are widely and deeply discussed. experience in memory and low-voltage designs in industry, bridging the different necessary technologies between memory, digital, and analog technologies, and even between DRAMs and SRAMs. A lot of knowledge that authors have acquired to date, and circuits that authors regard as important are covered from the basics to the state-of-the-art. Thus, the book is beneficial to students and engineers interested in ultra-low voltage nano-scale LSIs. Moreover, it is instructive not only for memory designers, but also for all digital and analog LSI designers who are the front edge of such LSI developments, since it is full of insight to develop such LSIs.