This book presents the theory behind software-implemented hardware fault tolerance, as well as the practical aspects needed to put it to work on real examples. By evaluating accurately the advantages and disadvantages of the already available approaches, the book provides a guide to developers willing to adopt software-implemented hardware fault tolerance in their applications. Moreover, the book identifies open issues for researchers willing to improve the already available techniques.

Software-Implemented Hardware Fault Tolerance addresses the innovative topic of software-implemented hardware fault tolerance (SIHFT), i.e., how to deal with faults affecting the hardware by only (or mainly) acting on the software.

The first SIHFT techniques were proposed and adopted several decades ago, but they have been the object of new interest in the past few years, mainly due to the need for developing low-cost safety-critical computer-based applications in fields such as automotive, biomedics, and telecommunications. Therefore, several new approaches to detect, and when possible correct, transient and permanent faults in the hardware have been recently proposed. These approaches are innovative (with respect to those proposed in the past) since they are of higher applicability (often starting from the source-level code of an application) and generality, being capable of coping with many different fault types. The book presents the theory behind software-implemented hardware fault tolerance, as well as the practical aspects related to put it at work on real examples. By evaluating accurately the advantages and disadvantages of the already available approaches, the book provides a guide to developers willing to adopt software-implemented hardware fault tolerance in their applications. Moreover, the book identifies open issues for researchers willing to improve the already available techniques.

New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.

SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue.

This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:

• modeling of bugs and defects;
• stimulus generation for validation and test purposes (including timing errors;
• design for testability.

This book contains extended and revised versions of the best papers presented at the 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, held in Abu Dhabi, United Arab Emirates, in August 2017. The 11 papers included in this book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the latest scientific and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) Design. On the occasion of the silver jubilee of the VLSI-SoC conference series the book also includes a special chapter that presents the history of the VLSI-SoC series of conferences and its relation with VLSI-SoC evolution since the early 80s up to the present.

New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.

SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue.

This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:

• modeling of bugs and defects;
• stimulus generation for validation and test purposes (including timing errors;
• design for testability.