This book serves as a single-source reference to the state-of-the-art in Internet of Things (IoT) platforms, services, tools, programming languages, and applications. In particular, the authors focus on IoT-related requirements such as low-power, time-to-market, connectivity, reliability, interoperability, security, and privacy. Authors discuss the question of whether we need new IoT standardization bodies or initiatives, toward a fully connected, cyber-physical world. Coverage includes the research outcomes of several, current European projects related to IoT platforms, services, APIs, tools, and applications.

This book constitutes the proceedings of the 14th International Conference on Applied Reconfigurable Computing, ARC 2018, held in Santorini, Greece, in May 2018. The 29 full papers and 22 short presented in this volume were carefully reviewed and selected from 78 submissions. In addition, the volume contains 9 contributions from research projects. The papers were organized in topical sections named: machine learning and neural networks; FPGA-based design and CGRA optimizations; applications and surveys; fault-tolerance, security and communication architectures; reconfigurable and adaptive architectures; design methods and fast prototyping; FPGA-based design and applications; and special session: research projects.

This book serves as a single-source reference to the state-of-the-art in Internet of Things (IoT) platforms, services, tools, programming languages, and applications. In particular, the authors focus on IoT-related requirements such as low-power, time-to-market, connectivity, reliability, interoperability, security, and privacy. Authors discuss the question of whether we need new IoT standardization bodies or initiatives, toward a fully connected, cyber-physical world. Coverage includes the research outcomes of several, current European projects related to IoT platforms, services, APIs, tools, and applications.

VLSI 2010 Annual Symposium will present extended versions of the best papers presented in ISVLSI 2010 conference. The areas covered by the papers will include among others: Emerging Trends in VLSI, Nanoelectronics, Molecular, Biological and Quantum Computing. MEMS, VLSI Circuits and Systems, Field-programmable and Reconfigurable Systems, System Level Design, System-on-a-Chip Design, Application-Specific Low Power, VLSI System Design, System Issues in Complexity, Low Power, Heat Dissipation, Power Awareness in VLSI Design, Test and Verification, Mixed-Signal Design and Analysis, Electrical/Packaging Co-Design, Physical Design, Intellectual property creating and sharing.

System Level Design of Reconfigurable Systems-on-Chip provides insight in the challenges and difficulties encountered during the design of reconfigurable Systems-on-Chip (SoCs). Reconfiguration is becoming an important part of System-on-Chip design to cope with the increasing demands for simultaneous flexibility and computational power.

The book focuses on system level design issues for reconfigurable SoCs, and provides information on reconfiguration aspects of complex SoCs and how they can be implemented in practice. It is divided in three parts. The first part provides background information and requirements on reconfigurable technologies and systems. The second one identifies existing methodological gaps, and introduces a design flow for developing reconfigurable Systems-on-Chip. The high level part of the design flow can be covered by two C++ based methodologies: one based on SystemC and one based on OCAPI-XL, both including appropriate extensions to handle reconfiguration issues. Finally, the third part of the book presents reconfigurable SoCs from the perspective of the designer, through three indicative case studies from the wireless and multimedia communication domain.

Dynamic System Reconfiguration in Heterogeneous Platforms defines the MORPHEUS platform that can join the performance density advantage of reconfigurable technologies and the easy control capabilities of general purpose processors. It consists of a System-on-Chip made of a scalable system infrastructure hosting heterogeneous reconfigurable accelerators, providing dynamic reconfiguration capabilities and data-stream management capabilities.

System Level Design Model with Reuse of System IP addresses system design by providing a framework for assessing and developing system design practices that observe and utilise reuse of system design know-how. The know-how accumulated in the companies represents an intellectual asset, or property ('IP').

The current situation regarding system design in general is, that the methods are insufficient, informally practised, and weakly supported by formal techniques and tools. Regarding system design reuse the methods and tools for exchanging system design data and know-how within companies are ad hoc and insufficient. The means available inside companies being already insufficient, there are actually no ways of exchanging between companies.

To establish means for systematic reuse, the required system design concepts are identified through an analysis of existing design flows, and their definitions are catalogued in the form of a glossary and taxonomy. The System Design Conceptual Model (SDCM) formalises the concepts and their relationships by providing meta-models for both the system design process (SDPM) and the system under design (SUDM). The models are generic enough so that they can be applied in various organisations and for various kinds of electronic systems. System design patterns are presented as example means for enhancing reuse. The characteristics of system-level IP, a list of heuristic criteria of system-IP reusability, and guidelines for assessing system IP reusability within a particular design flow provide a pragmatic view to reuse. An analysis of selected languages and formalisms, and guidelines for the analysis of system-level languages provides means for assessing how the expression and representation of system design concepts are supported by languages.

System Level Design Model with Reuse of System IP describes both a theoretical framework and various practical means for improving reuse in the design of complex systems. The information can be used in various ways in enhancing system design: Understanding system design, Analysing and assessing existing design flows, reuse practices and languages, Instantiating design flows for new design paradigms, Eliciting requirements for methods and tools, Organising teams, and Educating employees, partners and customers.

System Level Design of Reconfigurable Systems-on-Chip provides insight in the challenges and difficulties encountered during the design of reconfigurable Systems-on-Chip (SoCs). Reconfiguration is becoming an important part of System-on-Chip design to cope with the increasing demands for simultaneous flexibility and computational power.

The book focuses on system level design issues for reconfigurable SoCs, and provides information on reconfiguration aspects of complex SoCs and how they can be implemented in practice. It is divided in three parts. The first part provides background information and requirements on reconfigurable technologies and systems. The second one identifies existing methodological gaps, and introduces a design flow for developing reconfigurable Systems-on-Chip. The high level part of the design flow can be covered by two C++ based methodologies: one based on SystemC and one based on OCAPI-XL, both including appropriate extensions to handle reconfiguration issues. Finally, the third part of the book presents reconfigurable SoCs from the perspective of the designer, through three indicative case studies from the wireless and multimedia communication domain.

This book presents the perspective of the SYDIC-Telecom project on system design and reuse as perceived in the course of the research during 1999 - 2003. The initial problem statement of the research was formulated as follows: "The current situation regarding system design in general is, that the methods are insufficient, informally practiced, and weakly supported by formal techniques and tools. Regarding system reuse the methods and tools for exchanging system design data and know-how within companies are ad hoc and insufficient. The means available inside companies being already insufficient, there are actually no ways of exchanging between companies. Therefore, there hardly exists any system IP (Intellectual Property) industry. Although system design know-how is one of companies' main assets, it cannot be reused and capitalised effectively enough today. There is a lack of rational design flows supporting a design methodology based on reuse of IP, and few design tools to support it. Even guidelines on how to use existing tools in the design flow for this purpose often do not exist." The problem was known to be hard and the scope broad. The plan of attack was first to analyse the state-of-the-art and the state-of-the-practice, then to identify potential improvements, and finally to synthesise a formalised proposal for implementation. The approach was applied to different system-level issues, e.g. design flows, terminology, languages, reuse, design process and object of design.

Dynamic System Reconfiguration in Heterogeneous Platforms defines the MORPHEUS platform that can join the performance density advantage of reconfigurable technologies and the easy control capabilities of general purpose processors. It consists of a System-on-Chip made of a scalable system infrastructure hosting heterogeneous reconfigurable accelerators, providing dynamic reconfiguration capabilities and data-stream management capabilities.