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Systematic Design of Sigma-Delta Analog-to-Digital Converters
describes the issues related to the sigma-delta analog-to-digital
converters (ADCs) design in a systematic manner: from the top level
of abstraction represented by the filters defining signal and noise
transfer functions (STF, NTF), passing through the architecture
level where topology-related performance is calculated and
simulated, and finally down to parameters of circuit elements like
resistors, capacitors, and amplifier transconductances used in
individual integrators. The systematic approach allows the
evaluation of different loop filters (order, aggressiveness,
discrete-time or continuous-time implementation) with quantizers
varying in resolution. Topologies explored range from simple single
loops to multiple cascaded loops with complex structures including
more feedbacks and feedforwards. For differential circuits, with
switched-capacitor integrators for discrete-time (DT) loop filters
and active-RC for continuous-time (CT) ones, the passive integrator
components are calculated and the power consumption is estimated,
based on top-level requirements like harmonic distortion and noise
budget.
Systematic Design of Sigma-Delta Analog-to-Digital Converters
describes the issues related to the sigma-delta analog-to-digital
converters (ADCs) design in a systematic manner: from the top level
of abstraction represented by the filters defining signal and noise
transfer functions (STF, NTF), passing through the architecture
level where topology-related performance is calculated and
simulated, and finally down to parameters of circuit elements like
resistors, capacitors, and amplifier transconductances used in
individual integrators. The systematic approach allows the
evaluation of different loop filters (order, aggressiveness,
discrete-time or continuous-time implementation) with quantizers
varying in resolution. Topologies explored range from simple single
loops to multiple cascaded loops with complex structures including
more feedbacks and feedforwards. For differential circuits, with
switched-capacitor integrators for discrete-time (DT) loop filters
and active-RC for continuous-time (CT) ones, the passive integrator
components are calculated and the power consumption is estimated,
based on top-level requirements like harmonic distortion and noise
budget.
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