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Simulation of brain neurons in real-time using
biophysically-meaningful models is a pre-requisite for
comprehensive understanding of how neurons process information and
communicate with each other, in effect efficiently complementing
in-vivo experiments. In spiking neural networks (SNNs), propagated
information is not just encoded by the firing rate of each neuron
in the network, as in artificial neural networks (ANNs), but, in
addition, by amplitude, spike-train patterns, and the transfer
rate. The high level of realism of SNNs and more significant
computational and analytic capabilities in comparison with ANNs,
however, limit the size of the realized networks. Consequently, the
main challenge in building complex and biophysically-accurate SNNs
is largely posed by the high computational and data transfer
demands. Real-Time Multi-Chip Neural Network for Cognitive Systems
presents novel real-time, reconfigurable, multi-chip SNN system
architecture based on localized communication, which effectively
reduces the communication cost to a linear growth. The system use
double floating-point arithmetic for the most biologically accurate
cell behavior simulation, and is flexible enough to offer an easy
implementation of various neuron network topologies, cell
communication schemes, as well as models and kinds of cells. The
system offers a high run-time configurability, which reduces the
need for resynthesizing the system. In addition, the simulator
features configurable on- and off-chip communication latencies as
well as neuron calculation latencies. All parts of the system are
generated automatically based on the neuron interconnection scheme
in use. The simulator allows exploration of different system
configurations, e.g. the interconnection scheme between the
neurons, the intracellular concentration of different chemical
compounds (ions), which affect how action potentials are initiated
and propagate.
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Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers (Paperback, Edition.)
Jose Monteiro, Rene van Leuken
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R1,585
Discovery Miles 15 850
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Ships in 10 - 15 working days
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Welcome to the proceedings of the 19th International Workshop on
Power and TimingModeling, OptimizationandSimulation,
PATMOS2009.Overtheyears,
PATMOShasevolvedintoanimportantEuropeanevent, whereresearchersfrom
both industry and academia discuss and investigate the emerging
challenges in future and contemporary applications, design
methodologies, and tools required for the development of the
upcoming generations of integrated circuits and s- tems. PATMOS
2009 was organized by TU Delft, The Netherlands, with sp- sorship
by the NIRICT Design Lab and Cadence Design Systems, and technical
co-sponsorshipbytheIEEE.Furtherinformationabouttheworkshopisavailable
athttp: //ens.ewi.tudelft.nl/patmos09. The technical programof
PATMOS 2009 contained state-of-the-arttechnical contributions,
three invited keynotes, and a special session on SystemC-AMS
Extensions. The technical program focused on timing, performance,
and power consumption, as well as architectural aspects with
particular emphasis on m- eling, design, characterization,
analysis, and optimization in the nanometer era. The Technical
Program Committee, with the assistance of additional expert
reviewers, selected the 36 papers presented at PATMOS. The papers
were - ganized into 7 oral sessions (with a total of 26 papers) and
2 poster sessions (with a total of 10 papers). As is customary for
the PATMOS workshops, full papers were required for review, and a
minimum of three reviews were received per manuscr
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