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Designers of high-speed integrated circuits face a bewildering
array of choices and too often spend frustrating days tweaking
gates to meet speed targets. "Logical Effort: Designing Fast CMOS
Circuits" makes high speed design easier and more methodical,
providing a simple and broadly applicable method for estimating the
delay resulting from factors such as topology, capacitance, and
gate sizes. The brainchild of circuit and computer graphics pioneers Ivan
Sutherland and Bob Sproull, "logical effort" will change the way
you approach design challenges. This book begins by equipping you
with a sound understanding of the method's essential procedures and
concepts-so you can start using it immediately. Later chapters
explore the theory and finer points of the method and detail its
specialized applications.
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