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Since process variation and chip performance uncertainties have
become more pronounced as technologies scale down into the
nanometer regime, accurate and efficient modeling or
characterization of variations from the device to the architecture
level have become imperative for the successful design of VLSI
chips. This book provides readers with tools for variation-aware
design methodologies and computer-aided design (CAD) of VLSI
systems, in the presence of process variations at the nanometer
scale. It presents the latest developments for modeling and
analysis, with a focus on statistical interconnect modeling,
statistical parasitic extractions, statistical full-chip leakage
and dynamic power analysis considering spatial correlations,
statistical analysis and modeling for large global interconnects
and analog/mixed-signal circuits. Provides readers with timely,
systematic and comprehensive treatments of statistical modeling and
analysis of VLSI systems with a focus on interconnects, on-chip
power grids and clock networks, and analog/mixed-signal circuits;
Helps chip designers understand the potential and limitations of
their design tools, improving their design productivity; Presents
analysis of each algorithm with practical applications in the
context of real circuit design; Includes numerical examples for the
quantitative analysis and evaluation of algorithms presented.
Provides readers with timely, systematic and comprehensive
treatments of statistical modeling and analysis of VLSI systems
with a focus on interconnects, on-chip power grids and clock
networks, and analog/mixed-signal circuits; Helps chip designers
understand the potential and limitations of their design tools,
improving their design productivity; Presents analysis of each
algorithm with practical applications in the context of real
circuit design; Includes numerical examples for the quantitative
analysis and evaluation of algorithms presented.
This book provides comprehensive coverage of the recent advances in
symbolic analysis techniques for design automation of nanometer
VLSI systems. The presentation is organized in parts of
fundamentals, basic implementation methods and applications for
VLSI design. Topics emphasized include statistical timing and
crosstalk analysis, statistical and parallel analysis, performance
bound analysis and behavioral modeling for analog integrated
circuits. Among the recent advances, the Binary Decision Diagram
(BDD) based approaches are studied in depth. The BDD-based
hierarchical symbolic analysis approaches, have essentially broken
the analog circuit size barrier.
This book provides comprehensive coverage of the recent advances in
symbolic analysis techniques for design automation of nanometer
VLSI systems. The presentation is organized in parts of
fundamentals, basic implementation methods and applications for
VLSI design. Topics emphasized include statistical timing and
crosstalk analysis, statistical and parallel analysis, performance
bound analysis and behavioral modeling for analog integrated
circuits . Among the recent advances, the Binary Decision Diagram
(BDD) based approaches are studied in depth. The BDD-based
hierarchical symbolic analysis approaches, have essentially broken
the analog circuit size barrier.
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VLSI Design (Hardcover)
Esteban Tlelo-Cuautle, Sheldon X. D. Tan
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R4,366
R4,067
Discovery Miles 40 670
Save R299 (7%)
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Ships in 10 - 15 working days
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