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This state-of-the-art monograph presents a coherent survey of a
variety of methods and systems for formal hardware verification. It
emphasizes the presentation of approaches that have matured into
tools and systems usable for the actual verification of nontrivial
circuits. All in all, the book is a representative and
well-structured survey on the success and future potential of
formal methods in proving the correctness of circuits. The various
chapters describe the respective approaches supplying theoretical
foundations as well as taking into account the application
viewpoint. By applying all methods and systems presented to the
same set of IFIP WG10.5 hardware verification examples, a valuable
and fair analysis of the strenghts and weaknesses of the various
approaches is given.
Hardware verification is a hot topic in circuit and system design due to rising circuit complexity. This advanced textbook presents an almost complete overview of techniques for hardware verification. It covers all approaches used in existing tools, such as binary and word-level decision diagrams, symbolic methods for equivalence checking, and temporal logic model checking, and introduces the use of higher-order logic theorem proving for verifying circuit correctness. It enables the reader to understand the advantages and limitations of each technique. Each chapter contains an introduction and a summary as well as a section for the advanced reader. Thus a broad audience is addressed, from beginners in system design to experts.
This advanced textbook presents an almost complete overview of
techniques for hardware verification. It covers all approaches used
in existing tools, such as binary and word-level decision diagrams,
symbolic methods for equivalence and temporal logic model checking,
and introduces the use of higher-order logic theorem proving for
verifying circuit correctness. Each chapter contains an
introduction and a summary as well as a section for the advanced
reader, aiding an understanding of the advantages and limitations
of each technique. Backed by many examples and illustrations, this
text will appeal to a broad audience, from beginners in system
design to experts. XXXXXXX Neuer Text This is a complete overview
of existing techniques for hardware verification. It covers all
approaches used in existing verification tools, such as symbolic
methods for equivalence checking, temporal logic model checking,
and higher-order logic theorem proving for verifying circuit
correctness. The book helps readers to understand the advantages
and limitations of each technique. Each chapter contains a summary
as well as a section for the advanced reader.
CHARME'99 is the tenth in a series of working conferences devoted
to the dev- opment and use of leading-edge formal techniques and
tools for the design and veri?cation of hardware and systems.
Previous conferences have been held in Darmstadt (1984), Edinburgh
(1985), Grenoble (1986), Glasgow (1988), Leuven (1989), Torino
(1991), Arles (1993), Frankfurt (1995) and Montreal (1997). This
workshop and conference series has been organized in cooperation
with IFIP WG 10. 5. It is now the biannual counterpart of FMCAD,
which takes place every even-numbered year in the USA. The 1999
event took place in Bad Her- nalb, a resort village located in the
Black Forest close to the city of Karlsruhe. The validation of
functional and timing behavior is a major bottleneck in current
VLSI design systems. A predominantly academic area of study until a
few years ago, formal design and veri?cation techniques are now
migrating into industrial use. The aim of CHARME'99 is to bring
together researchers and users from academia and industry working
in this active area of research. Two invited talks illustrate major
current trends: the presentation by Gerard Berry (Ecole des Mines
de Paris, Sophia-Antipolis, France) is concerned with the use of
synchronous languages in circuit design, and the talk given by
Peter Jansen (BMW, Munich, Germany) demonstrates an application of
formal methods in an industrial environment. The program also
includes 20 regular presentations and 12 short presentations/poster
exhibitions that have been selected from the 48 submitted papers."
This volume presents the proceedings of the Second International
Conference on Theorem Provers in Circuit Design (TPCD '94) jointly
organized by the Forschungszentrum Informatik (University of
Karlsruhe) and IFIP Working Group 10.2 in Bad Herrenalb, Germany in
September 1994.
The 19 papers included are thoroughly revised versions of the
submissions selected for presentation at the conference and address
all current aspects of theorem provers in circuit design.
Particular emphasis is given to benchmark-circuits for hardware
verification; tutorials on two popular theorem provers are
included.
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