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The proliferation and growth of Electronic Design Automation (EDA)
has spawned many diverse and interesting technologies. One of the
most prominent of these technologies is the VHSIC Hardware
Description Language, or VHDL. VHDL permits designers of digital
modules, components, systems, and even networks to describe their
designs both structurally and behaviorally. VHDL also allows
simulation of the designs in order to investigate their performance
prior to actually implementing them in hardware. Having gained the
ability to simulate designs once encoded in VHDL, designers were
naturally confronted with the issue of testing these designs. VHDL
did not explicitly address the requirement to insert particular
digital waveforms, often termed test vectors or patterns, or to
subsequently assess the correctness of the response from some
digital entity. In a distributed design environment, or even in an
isolated one where the design was subject to review or scrutiny by
another organization, de-facto methods of testing and evaluating
results proved faulty. The reason was a lack of
standardization.When organization A designed a circuit and tested
it with their self-developed test tools it had a certain behavior.
When it was delivered to organization B and B tested it using their
test tools, the behavior was different. Was the fault in the
circuit, in A's tools, or in B's tools? The only way to resolve
this was for both organizations to agree on a test apparatus,
validate its correctness and use it consistently. While VHDL was an
IEEE standard language, and consistency among myriad designers was
fairly well guaranteed, no such standard existed for test waveform
generation and assessment. Hence, the value of standardization in
the design language was being negated by the lack of such a
standard for testing. The Waveform and Vector Exchange
Specification, or WAVES, was conceived and designed to solve this
testing problem -- and it has. Being both a subset of VHDL itself,
as well as an IEEE standard, it guarantees both conformity among
multiple applications and easy integration with VHDL units under
test (UUTs). Using WAVES and VHDL for Effective Design and Testing
will serve many purposes.For the WAVES beginner, its tutorial will
make the application of WAVES in typical, standard usage
straightforward and convenient. For the more advanced user, the
advanced topics will provide insight into the nuances of these
useful capabilities. For all users, the tools, templates and
examples given in the chapters, as well as on the companion disk,
will provide a practical starting foundation for using WAVES and
VHDL.
2 Concept ( Tools * Specification ( Tools + Design Stages ( Tools *
Implementation ( Tools Figure 1-1. A nominal, multi-stage
development process From that beginning, we have progressed to the
point where the EDA community at large, including both users and
developers of the tools, are interested in more unified
environments. Here, the notion is that the tools used at the
various stages in the development process need to be able to
complement each other, and to communicate with one another
efficiently using effective file exchange capabilities.
Furthermore, the idea of capturing all the tool support needed for
an EDA development into a unified support environment is now
becoming a reality. This reality is evidenced by some of the EDA
suites we now see emerging, wherein several tool functions are
integrated under a common graphical user interface (GUI), with
supporting file exchange and libraries to enable all tool functions
to operate effectively and synergistically. This concept, which we
illustrate in Figure 1- 2, is the true future ofEDA.
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