This unique book covers the fundamental principle of electron diffraction, basic instrumentation of RHEED, definitions of textures in thin films and nanostructures, mechanisms and control of texture formation, and examples of RHEED transmission mode measurements of texture and texture evolution of thin films and nanostructures. Also presented is a new application of RHEED in the transmission mode called RHEED pole figure technique that can be used to monitor the texture evolution in thin film growth and nanostructures and is not limited to single crystal epitaxial film growth. Details of the construction of RHEED pole figures and the interpretation of observed pole figures are presented. Materials covered include metals, semiconductors, and thin insulators. This book also: Presents a new application of RHEED in the transmission mode Introduces a variety of textures from metals, semiconductors, compound semiconductors, and their characteristics in RHEED pole figures Provides examples of RHEED measurements of texture and texture evolution, construction of RHEED pole figures, and interpretation of observed pole figures RHEED Transmission Mode and Pole Figures: Thin Film and Nanostructure Texture Analysis is ideal for researchers in materials science and engineering and nanotechnology.

Chemical Vapor Deposition Polymerization - The Growth and Properties of Parylene Thin Films is intended to be valuable to both users and researchers of parylene thin films. It should be particularly useful for those setting up and characterizing their first research deposition system. It provides a good picture of the deposition process and equipment, as well as information on system-to-system variations that is important to consider when designing a deposition system or making modifications to an existing one. Also included are methods to characterizae a deposition system's pumping properties as well as monitor the deposition process via mass spectrometry. There are many references that will lead the reader to further information on the topic being discussed.
This text should serve as a useful reference source and handbook for scientists and engineers interested in depositing high quality parylene thin films.

Diffusion Barrier Stack - 5 nm -3 nm -2 nm :. . . -. . . . : . . O. 21-lm Figure 2: Schematic representing a cross-sectional view of the topography that is encountered in the processing of integrated circuits. (Not to scale) these sub-micron sized features is depicted in Fig. 2. The role of the diffusion barrier is to prevent the diffusion of metallic ions into the interlayer dielectric (lLD). Depending on the technology, in particular the choice of the ILD and the metal interconnect, the diffusion barrier may be Ti, Ta, TiN, TaN, or a multi-layered structure of these materials. The adhesion of the barrier to the dielectric, the conformality of the barrier to the feature, the physical structure of the film, and the chemical composition of the film are key issues that are determined in part by the nature of the deposition process. Likewise, after the growth of the barrier, a conducting layer (the seed layer) is needed for subsequent filling of the trench by electrochemical deposition. Again, the growth process must be able to deposit a film that is continuous along the topography of the sub-micron sized features. Other factors of concern are the purity and the texture of the seed layer, as both of these factors influence the final resistivity of the metallic interconnect. Sputter-deposited coatings are also commonly employed for their electro-optical properties. For example, an electrochromic glazing is used to control the flux of light that is transmitted through a glazed material.

Metal-dielectric interfaces are ubiquitous in modern electronics. As advanced gigascale electronic devices continue to shrink, the stability of these interfaces is becoming an increasingly important issue that has a profound impact on the operational reliability of these devices. In this book, the authors present the basic science underlying the thermal and electrical stability of metal-dielectric interfaces and its relationship to the operation of advanced interconnect systems in gigascale electronics. Interface phenomena, including chemical reactions between metals and dielectrics, metallic-atom diffusion, and ion drift, are discussed based on fundamental physical and chemical principles. Schematic diagrams are provided throughout the book to illustrate interface phenomena and the principles that govern them. Metal-Dielectric Interfaces in Gigascale Electronics provides a unifying approach to the diverse and sometimes contradictory test results that are reported in the literature on metal-dielectric interfaces. The goal is to provide readers with a clear account of the relationship between interface science and its applications in interconnect structures. The material presented here will also be of interest to those engaged in field-effect transistor and memristor device research, as well as university researchers and industrial scientists working in the areas of electronic materials processing, semiconductor manufacturing, memory chips, and IC design.

The focus of this book is on modeling and simulations used in research on the morphological evolution during film growth. The authors emphasize the detailed mathematical formulation of the problem. The book will enable readers themselves to set up a computational program to investigate specific topics of interest in thin film deposition. It will benefit those working in any discipline that requires an understanding of thin film growth processes.

This book focuses on the experimental and theoretical aspects of the time-dependent breakdown of advanced dielectric films used in gigascale electronics. Coverage includes the most important failure mechanisms for thin low-k films, new and established experimental techniques, recent advances in the area of dielectric failure, and advanced simulations/models to resolve and predict dielectric breakdown, all of which are of considerable importance for engineers and scientists working on developing and integrating present and future chip architectures. The book is specifically designed to aid scientists in assessing the reliability and robustness of electronic systems employing low-k dielectric materials such as nano-porous films. Similarly, the models presented here will help to improve current methodologies for estimating the failure of gigascale electronics at device operating conditions from accelerated lab test conditions. Numerous graphs, tables, and illustrations are included to facilitate understanding of the topics. Readers will be able to understand dielectric breakdown in thin films along with the main failure modes and characterization techniques. In addition, they will gain expertise on conventional as well as new field acceleration test models for predicting long term dielectric degradation.

This unique book covers the fundamental principle of electron diffraction, basic instrumentation of RHEED, definitions of textures in thin films and nanostructures, mechanisms and control of texture formation, and examples of RHEED transmission mode measurements of texture and texture evolution of thin films and nanostructures. Also presented is a new application of RHEED in the transmission mode called RHEED pole figure technique that can be used to monitor the texture evolution in thin film growth and nanostructures and is not limited to single crystal epitaxial film growth. Details of the construction of RHEED pole figures and the interpretation of observed pole figures are presented. Materials covered include metals, semiconductors, and thin insulators. This book also: Presents a new application of RHEED in the transmission mode Introduces a variety of textures from metals, semiconductors, compound semiconductors, and their characteristics in RHEED pole figures Provides examples of RHEED measurements of texture and texture evolution, construction of RHEED pole figures, and interpretation of observed pole figures RHEED Transmission Mode and Pole Figures: Thin Film and Nanostructure Texture Analysis is ideal for researchers in materials science and engineering and nanotechnology.

Diffusion Barrier Stack - 5 nm -3 nm -2 nm :. . . -. . . . : . . O. 21-lm Figure 2: Schematic representing a cross-sectional view of the topography that is encountered in the processing of integrated circuits. (Not to scale) these sub-micron sized features is depicted in Fig. 2. The role of the diffusion barrier is to prevent the diffusion of metallic ions into the interlayer dielectric (lLD). Depending on the technology, in particular the choice of the ILD and the metal interconnect, the diffusion barrier may be Ti, Ta, TiN, TaN, or a multi-layered structure of these materials. The adhesion of the barrier to the dielectric, the conformality of the barrier to the feature, the physical structure of the film, and the chemical composition of the film are key issues that are determined in part by the nature of the deposition process. Likewise, after the growth of the barrier, a conducting layer (the seed layer) is needed for subsequent filling of the trench by electrochemical deposition. Again, the growth process must be able to deposit a film that is continuous along the topography of the sub-micron sized features. Other factors of concern are the purity and the texture of the seed layer, as both of these factors influence the final resistivity of the metallic interconnect. Sputter-deposited coatings are also commonly employed for their electro-optical properties. For example, an electrochromic glazing is used to control the flux of light that is transmitted through a glazed material.

The focus of this book is on modeling and simulations used in research on the morphological evolution during film growth. The authors emphasize the detailed mathematical formulation of the problem. The book will enable readers themselves to set up a computational program to investigate specific topics of interest in thin film deposition. It will benefit those working in any discipline that requires an understanding of thin film growth processes.

Chemical Vapor Deposition Polymerization - The Growth and Properties of Parylene Thin Films is intended to be valuable to both users and researchers of parylene thin films. It should be particularly useful for those setting up and characterizing their first research deposition system. It provides a good picture of the deposition process and equipment, as well as information on system-to-system variations that is important to consider when designing a deposition system or making modifications to an existing one. Also included are methods to characterizae a deposition system's pumping properties as well as monitor the deposition process via mass spectrometry. There are many references that will lead the reader to further information on the topic being discussed.
This text should serve as a useful reference source and handbook for scientists and engineers interested in depositing high quality parylene thin films.

Metal-dielectric interfaces are ubiquitous in modern electronics. As advanced gigascale electronic devices continue to shrink, the stability of these interfaces is becoming an increasingly important issue that has a profound impact on the operational reliability of these devices. In this book, the authors present the basic science underlying the thermal and electrical stability of metal-dielectric interfaces and its relationship to the operation of advanced interconnect systems in gigascale electronics. Interface phenomena, including chemical reactions between metals and dielectrics, metallic-atom diffusion, and ion drift, are discussed based on fundamental physical and chemical principles. Schematic diagrams are provided throughout the book to illustrate interface phenomena and the principles that govern them. Metal-Dielectric Interfaces in Gigascale Electronics provides a unifying approach to the diverse and sometimes contradictory test results that are reported in the literature on metal-dielectric interfaces. The goal is to provide readers with a clear account of the relationship between interface science and its applications in interconnect structures. The material presented here will also be of interest to those engaged in field-effect transistor and memristor device research, as well as university researchers and industrial scientists working in the areas of electronic materials processing, semiconductor manufacturing, memory chips, and IC design.