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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings (Paperback, 2005 ed.)
Vassilis Paliouras, Johan Vounckx, Diederik Verkest
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R3,408
Discovery Miles 34 080
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Ships in 10 - 15 working days
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Welcome to the proceedings of PATMOS 2005, the 15th in a series of
international
workshops.PATMOS2005wasorganizedbyIMECwithtechnicalco-sponsorshipfrom
the IEEE Circuits and Systems Society. Over the years, PATMOS has
evolved into an important European event, where - searchers from
both industry and academia discuss and investigate the emerging ch-
lenges in future and contemporary applications, design
methodologies, and tools - quired for the developmentof
upcominggenerationsof integrated circuits and systems. The
technical program of PATMOS 2005 contained state-of-the-art
technical contri- tions, three invited talks, a special session on
hearing-aid design, and an embedded - torial. The technical program
focused on timing, performance and power consumption, as well as
architectural aspects with particular emphasis on modeling, design,
char- terization, analysis and optimization in the nanometer era.
The Technical Program Committee, with the assistance of additional
expert revi- ers, selected the 74 papers to be presented at PATMOS.
The papers were divided into 11 technical sessions and 3 poster
sessions. As is always the case with the PATMOS workshops, the
review process was anonymous, full papers were required, and
several reviews were carried out per paper. Beyond the
presentations of the papers, the PATMOS technical program was -
riched by a series of speeches offered by world class experts, on
important emerging research issues of industrial relevance. Prof.
Jan Rabaey, Berkeley, USA, gave a talk on "Traveling the Wild
Frontier of Ulta Low-Power Design," Dr. Sung Bae Park, S- sung,
gave a presentation on "DVL (Deep Low Voltage): Circuits and
Devices," Prof.
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Integrated Circuit and System Design - Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings (Paperback, 2004 ed.)
Enrico Macii, Vassilis Paliouras, Odysseas Koufopavlou
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R4,753
Discovery Miles 47 530
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Ships in 10 - 15 working days
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WelcometotheproceedingsofPATMOS2004, thefourteenthinaseriesofint-
national workshops. PATMOS 2004 was organized by the University of
Patras with technical co-sponsorship from the IEEE Circuits and
Systems Society. Over the years, the PATMOS meeting has evolved
into an important - ropean event, where industry and academia meet
to discuss power and timing aspects in modern integrated circuit
and system design. PATMOS provides a forum for researchers to
discuss and investigate the emerging challenges in - sign
methodologies and tools required to develop the upcoming
generations of integrated circuits and systems. We realized this
vision this year by providing a technical program that contained
state-of-the-art technical contributions, a keynote speech, three
invited talks and two embedded tutorials. The technical program
focused on timing, performance and power consumption, as well as
architectural aspects, with particular emphasis on modelling,
design, charac- rization, analysis and optimization in the
nanometer era. This year a record 152 contributions were received
to be considered for p- sible presentation at PATMOS. Despite the
choice for an intense three-day m- ting, only 51 lecture papers and
34 poster papers could be accommodated in the single-track
technical program. The Technical Program Committee, with the -
sistance of additional expert reviewers, selected the 85 papers to
be presented at PATMOS and organized them into 13 technical
sessions. As was the case with the PATMOS workshops, the review
process was anonymous, full papers were required, and several
reviews were received per manuscript
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