Rapid energy estimation for energy efficient applications using field-programmable gate arrays (FPGAs) remains a challenging research topic. Energy dissipation and efficiency have prevented the widespread use of FPGA devices in embedded systems, where energy efficiency is a key performance metric. Helping overcome these challenges, Energy Efficient Hardware-Software Co-Synthesis Using Reconfigurable Hardware offers solutions for the development of energy efficient applications using FPGAs. The book integrates various high-level abstractions for describing hardware and software platforms into a single, consistent application development framework, enabling users to construct, simulate, and debug systems. Based on these high-level concepts, it proposes an energy performance modeling technique to capture the energy dissipation behavior of both the reconfigurable hardware platform and the target applications running on it. The authors also present a dynamic programming-based algorithm to optimize the energy performance of an application running on a reconfigurable hardware platform. They then discuss an instruction-level energy estimation technique and a domain-specific modeling technique to provide rapid and fairly accurate energy estimation for hardware-software co-designs using reconfigurable hardware. The text concludes with example designs and illustrative examples that show how the proposed co-synthesis techniques lead to a significant amount of energy reduction. This book explores the advantages of using reconfigurable hardware for application development and looks ahead to future research directions in the field. It outlines the range of aspects and steps that lead to an energy efficient hardware-software application synthesis using FPGAs.

at the distributed virtual Program Committee meeting. Each paper's review recomm- dationswere carefully checkedfor consistency; in many instances, the Vice Chairs read the papers themselves when the reviews did not seem suf?cient to make a decision. Throughout the reviewing process, I received a tremendous amount of help and advice from General Co-chair Manish Parashar, Steering Chair Viktor Prasanna, and last year's Program Chair Srinivas Aluru; I am very grateful to them. My thanks also go to the Publications Chair Sushil Prasad for his outstanding efforts in putting the proceedings together. Finally, I thank all the authors for their contributions to a hi- quality technical program. I wish all the attendees a very enjoyable and informative meeting. December 2008 P. Sadayappan Message from the General Co-chairs and the Vice General Co-chairs On behalf of the organizers of the 15th International Conference on High-Performance Computing(HiPC), it is our pleasureto present these proceedingsand we hopeyou will ?nd them exciting and rewarding. TheHiPCcallforpapers, onceagain, receivedanoverwhelmingresponse, attracting 317submissionsfrom27countries.P.Sadayappan, theProgramChair, andthe Program Committee worked with remarkablededication to put together an outstandingtechnical program consisting of the 46 papers that appear in these proceedings.

This book constitutes the refereed proceedings of the 14th International Conference on High-Performance Computing, HiPC 2007, held in Goa, India, in December 2007.

The 53 revised full papers presented together with the abstracts of 5 keynote talks were carefully reviewed and selected from 253 submissions. The papers are organized in topical sections on applications on I/O and FPGAs, microarchitecture and multiprocessor architecture, applications of novel architectures, system software, scheduling, energy-aware computing, P2P and internet applications, communication and routing, cluster and grid applications, as well as mobile computing.

This book constitutes the refereed proceedings of the 13th International Conference on High-Performance Computing, HiPC 2006, held in Bangalore, India in December 2006.

The 52 revised full papers presented together with the abstracts of 7 invited talks were carefully reviewed and selected from 335 submissions. The papers are organized in topical sections on scheduling and load balancing, architectures, network and distributed algorithms, application software, network services, applications, ad-hoc networks, systems software, sensor networks and performance evaluation, as well as routing and data management algorithms.

to acknowledge the dedicated effort put forth by the Vice-Chairs: Michael A. Bender (Algorithms), Zhiwei Xu (Applications), Jose Duato (Architecture), M. Cristina Pinotti (Communication Networks), and Satoshi Matsuoka (System Software). Without their help and timely work, the quality of this program would not be as high nor would the process have run so smoothly. I thank the other organizers who have contributed to assembling this program, - cludingthose who organizedthe keynotes, tutorials, workshops, awards, poster session, industry exhibits, and those who performed the administrative functions that have been essential to the success of this conference. The work of Sushil K. Prasad in putting - gethertheconferenceproceedingsisalsoacknowledged, aswell asthesupportprovided by Kamesh Madduri and Vaddadi Chandu, Ph.D. students at Georgia Institute of Te- nology, and Vipin Sachdeva, M.S. student at the Universityof New Mexico, in assisting with the EDAS online paper submission and evaluation software. Last, but certainly not least, I express heart-felt thanks to our General Co-chairs, Manish Parashar and V. Sridhar; Steering Chair, Viktor Prasanna; and to the Vice-General Chair, Rajendra V. Boppana; for all their useful advice. Lastly, I thank the Conference General Co-chairs for allowing me to serve our c- munity as the Program Chair of this high-quality international conference. It has been my pleasure to correspond with so many of you, and I personally welcome you to Go

The book constitutes the refereed proceedings of the First International Conference on Distributed Computing in Sensor Systems, DCOSS 2005, held in Marina del Rey, California, USA in June/July 2005.

The 26 revised full papers presented were carefully reviewed and selected from 85 submissions; also included are the abstracts of 3 invited talks, 2 short papers, 9 invited poster abstracts, and 10 contributed abstracts.The papers address all current aspects of distributed computing issues in large-scale networked sensor systems, including systematic design techniques and tools, algorithms, and applications.

timely work, the quality of this program would not be as high nor would the process have run so smoothly. Ialsowishtothanktheothersupportingcastmemberswhohelpedinputtingtogether thisprogram, includingthosewhoorganizedthekeynotes, tutorials, workshops, awards, poster session, industrial track session, and those who performed the administrative functions that are essential to the success of this conference. The work of Sushil K. Prasad in putting together the conference proceedings is also acknowledged, as well as the support provided by Mathieu Jan and Sebastien Monnet, PhD students at IRISA, in maintaining the CyberChair online paper submission and evaluation software. Last, but certainly not least, I express heartfelt thanks to our General Co-chairs, Viktor Prasanna and Uday Shukla, and to the Vice-General Chair, David A. Bader, for all their useful advice. The preparation of this conference was unfortunately marked by a very sad and unexpectedevent: thesuddendemiseofDr.UdayShukla, whowasastrongsupporterof HiPC over the past ten years. He passed away on July 20, 2004 after a very brief illness. Dr. Shukla had been involved in organizing HiPC since the beginning. In addition to his encouragement in organizing HiPC, Dr. Shukla was a strong supporter of research activitiesincomputerscienceandinformationtechnologyinIndia.Wewillmissafriend of HiP

Message from the Steering Chair It was my pleasure to welcome attendees to the 10th International Conference on High-Performance Computing and to Hyderabad, an emerging center of IT activities in India. We are indebted to Timothy Pinkston for his superb e?orts as program chair in organizing an excellent technical program. We received a record number of submissions this year. Over the past year, I discussed the meeting details with Timothy. I am grateful to him for his thoughtful inputs. Many volunteers helped to organize the meeting. In addition, I was glad to welcome Rajesh Gupta as Keynote Chair, Atul Negi as Student Scholarships Chair, and Sushil Prasad as Proceedings Chair. I look forward to their cont- butions for the continued success of the meeting series. Sushil Prasad did an excellent job in bringing out these proceedings. Kamal Karlapalem assisted us with local arrangements at IIIT, Hyderabad. Dheeraj Sanghi took on the r- ponsibility of focussed publicity for the meeting within India. Vijay Keshav of Intel India, though not listed as a volunteer, provided me with many pointers for bringing the India-based high-performance computing vendors to the meeting. I would like to thank M. Vidyasagar for agreeing to host the meeting in Hyderabad and for his assistance with the local arrangements. Continuing the tradition set at last year's meeting, several workshops were organized by volunteers. These workshops were coordinated by C.P. Ravikumar. Healsovolunteeredtoputtogethertheworkshopproceedings, andSushilPrasad assisted him in this.

This book constitutes the refereed proceedings of the 9th International Conference on High Performance Computing, HiPC 2002, held in Bangalore, India in December 2002. The 57 revised full contributed papers and 9 invited papers presented together with various keynote abstracts were carefully reviewed and selected from 145 submissions. The papers are organized in topical sections on algorithms, architecture, systems software, networks, mobile computing and databases, applications, scientific computation, embedded systems, and biocomputing.

This book constitutes the refereed proceedings of the 8th International Conference on High Performance Computing, HiPC 2001, held in Hyderabad, India, in December 2001.The 29 revised full papers presented together with 5 keynote papers and 3 invited papers were carefully reviewed and selected from 108 submissions. The papers are organized in topical sections on algorithms, applications, architecture, systems software, communications networks, and challenges in networking.

This book constitutes the refereed proceedings of the 7th International Conference on High Performance Computing, HiPC 2000, held in Bangalore, India in December 2000. The 46 revised papers presented together with five invited contributions were carefully reviewed and selected from a total of 127 submissions. The papers are organized in topical sections on system software, algorithms, high-performance middleware, applications, cluster computing, architecture, applied parallel processing, networks, wireless and mobile communication systems, and large scale data mining.

These are the proceedings of the Sixth International Conference on High Performance Computing (HiPC'99) held December 17-20 in Calcutta, India. The meeting serves as a forum for presenting current work by researchers from around the world as well as highlighting activities in Asia in the high performance computing area. The meeting emphasizes both the design and the analysis of high performance computing systems and their scientific, engineering, and commercial applications. Topics covered in the meeting series include: Parallel Algorithms Scientific Computation Parallel Architectures Visualization Parallel Languages & Compilers Network and Cluster Based Computing Distributed Systems Signal & Image Processing Systems Programming Environments Supercomputing Applications Memory Systems Internet and WWW-based Computing Multimedia and High Speed Networks Scalable Servers We would like to thank Alfred Hofmann and Ruth Abraham of Springer-Verlag for their excellent support in bringing out the proceedings. The detailed messages from the steering committee chair, general co-chair and program chair pay tribute to numerous volunteers who helped us in organizing the meeting. October 1999 Viktor K. Prasanna Bhabani Sinha Prithviraj Banerjee Message from the Steering Chair It is my pleasure to welcome you to the Sixth International Conference on High Performance Computing. I hope you enjoy the meeting, the rich cultural heritage of Calcutta, as well as the mother Ganges, "the river of life."

Rapid energy estimation for energy efficient applications using field-programmable gate arrays (FPGAs) remains a challenging research topic. Energy dissipation and efficiency have prevented the widespread use of FPGA devices in embedded systems, where energy efficiency is a key performance metric. Helping overcome these challenges, Energy Efficient Hardware-Software Co-Synthesis Using Reconfigurable Hardware offers solutions for the development of energy efficient applications using FPGAs. The book integrates various high-level abstractions for describing hardware and software platforms into a single, consistent application development framework, enabling users to construct, simulate, and debug systems. Based on these high-level concepts, it proposes an energy performance modeling technique to capture the energy dissipation behavior of both the reconfigurable hardware platform and the target applications running on it. The authors also present a dynamic programming-based algorithm to optimize the energy performance of an application running on a reconfigurable hardware platform. They then discuss an instruction-level energy estimation technique and a domain-specific modeling technique to provide rapid and fairly accurate energy estimation for hardware-software co-designs using reconfigurable hardware. The text concludes with example designs and illustrative examples that show how the proposed co-synthesis techniques lead to a significant amount of energy reduction. This book explores the advantages of using reconfigurable hardware for application development and looks ahead to future research directions in the field. It outlines the range of aspects and steps that lead to an energy efficient hardware-software application synthesis using FPGAs.