In order to comply with the requirements on the confidential communications and the information securities for handheld devices in the market, it is necessary for us to introduce the information crypto technology to the embedded devices. The challenge we have to face is to operate the system smoothly under the constraints of low cost, low power consumption, and high efficiency while transmitting the cryptosystem technique into the embedded system platform in mobile devices. In this thesis, we will combine a virtual microprocessor of the verification and AMBA bus to elaborate an embedded system model that is capable of shortening the testing time of the global system and calculating the performance for various types of microprocessors. An AES hardware of power management technology and Chaos key evolved module would be integrated to create an embedded cryptosystem. The results of our experiments would offer a valuable reference for the future planning and evaluation for the consuming electronic product based public and information security system.

In this work, we present a fourth-order cascade-of-integrators feedback Sigma-Delta A/D converter. We use Oversampling and Noise-Shaping techniques to earn a higher resolution than that in the Nyquist-Rate A/D converters. A generic method is presented to make the system stabilized. In order to fix the zeros and poles in the unit circle, we use MATLAB to design the Butterworth high pass filter, and then the coefficients could be obtained. We present a complete design flow to decrease the time of the design. By applying this method, a fourth-order Sigma-Delta A/D converter is implemented by TSMC 0.35 m 2P4M Mixed-Signal Polycide process provided by National Chip Implementation Center. The circuit specification is as follows: the supply voltage is 3.3 V, the sampling rate is 256, the signal bandwidth is 20k Hz, the working frequency is 10.24Meg Hz, an SNR, 75.7dB is attained, and the total power consumption is 20.3 mW.