Reconfigurable computing techniques and adaptive systems are some of the most promising architectures for microprocessors. Reconfigurable and Adaptive Computing: Theory and Applications explores the latest research activities on hardware architecture for reconfigurable and adaptive computing systems. The first section of the book covers reconfigurable systems. The book presents a software and hardware codesign flow for coarse-grained systems-on-chip, a video watermarking algorithm for the H.264 standard, a solution for regular expressions matching systems, and a novel field programmable gate array (FPGA)-based acceleration solution with MapReduce framework on multiple hardware accelerators. The second section discusses network-on-chip, including an implementation of a multiprocessor system-on-chip platform with shared memory access, end-to-end quality-of-service metrics modeling based on a multi-application environment in network-on-chip, and a 3D ant colony routing (3D-ACR) for network-on-chip with three different 3D topologies. The final section addresses the methodology of system codesign. The book introduces a new software-hardware codesign flow for embedded systems that models both processors and intellectual property cores as services. It also proposes an efficient algorithm for dependent task software-hardware codesign with the greedy partitioning and insert scheduling method (GPISM) by task graph.

A hands-on guide to writing a Message Passing Interface, this book takes the reader on a tour across major MPI implementations, best optimization techniques, application relevant usage hints, and a historical retrospective of the MPI world, all based on a quarter of a century spent inside MPI. Readers will learn to write MPI implementations from scratch, and to design and optimize communication mechanisms using pragmatic subsetting as the guiding principle. Inside the Message Passing Interface also covers MPI quirks and tricks to achieve best performance. Dr. Alexander Supalov created the Intel Cluster Tools product line, including the Intel MP Library that he designed and led between 2003 and 2015. He invented the common MPICH ABI and also guided Intel efforts in the MPI Forum during the development of the MPI-2.1, MPI-2.2, and MPI-3 standards. Before that, Alexander designed new finite-element mesh-generation methods, contributing to the PARMACS and PARASOL interfaces, and developed the first full MPI-2 and IMPI implementations in the world. He graduated from the Moscow Institute of Physics and Technology in 1990, and earned his PhD in applied mathematics at the Institute of Numerical Mathematics of the Russian Academy of Sciences in 1995. Alexander holds 26 patents (more pending worldwide).

Focusing on the use of the UEFI Shell and its recently released formal specification, this book unlocks a wide range of usage models which can help people best utilize the shell solutions. This text also expands on the obvious intended utilization of the shell and explains how it can be used in various areas such as security, networking, configuration, and other anticipated uses such as manufacturing, diagnostics, etc. Among other topics, Harnessing the UEFI Shell demonstrates how to write Shell scripts, how to write a Shell application, how to use provisioning options and more. Since the Shell is also a UEFI component, the book will make clear how the two things interoperate and how both Shell developers as well as UEFI developers can dip into the other's field to further expand the power of their solutions. Harnessing the UEFI Shell is authored by the three chairs of the UEFI working sub-teams, Michael Rothman (Intel, chair of the UEFI Configuration and UEFI Shell sub-teams), Vincent Zimmer (Intel, chair of the UEFI networking sub-team and security sub-team), and Tim Lewis (Insyde Software, chair of the UEFI security sub-team). This book is perfect for any OEMs that ship UEFI-based solutions (which is all of the MNCs such as IBM, Dell, HP, Apple, etc.), software developers who are focused on delivering solutions targeted to manufacturing, diagnostics, hobbyists, or stand-alone kiosk environments.

This book provides an overview of modern boot firmware, including the Unified Extensible Firmware Interface (UEFI) and its associated EFI Developer Kit II (EDKII) firmware. The authors have each made significant contributions to developments in these areas. The reader will learn to use the latest developments in UEFI on modern hardware, including open source firmware and open hardware designs. The book begins with an exploration of interfaces exposed to higher-level software and operating systems, and commences to the left of the boot timeline, describing the flow of typical systems, beginning with the machine restart event. Software engineers working with UEFI will benefit greatly from this book, while specific sections of the book address topics relevant for a general audience: system architects, pre-operating-system application developers, operating system vendors (loader, kernel), independent hardware vendors (such as for plug-in adapters), and developers of end-user applications. As a secondary audience, project technical leaders or managers may be interested in this book to get a feel for what their engineers are doing. The reader will find: An overview of UEFI and underlying Platform Initialization (PI) specifications How to create UEFI applications and drivers Workflow to design the firmware solution for a modern platform Advanced usages of UEFI firmware for security and manageability

With the introduction of WAP in Europe and I-mode in Japan, mobile terminals took their first steps out of the world of mobile telephony and into the world of mobile data. At the same time, the shift from 2nd generation to 3rd generation cellular technology has increased the potential data rate available to mobile users by tenfold as well as shifting data transport from circuit switched to packet data. These fundamental shifts in nature and the quantity of data available to mobile users has led to an explosion in the number of applications being developed for future digital terminal devices. Though these applications are diverse they share a common need for complex Digital Signal Processing (DSP) and in most cases benefit from the use of programmable DSPs (Digital Signal Processors).

• Features contributions from experts who discuss the implementation and applications of programmable DSPs

• Includes detailed introductions to speech coding, speech recognition, video and audio compression, biometric identification and their application for mobile communications devices

• Discusses the alternative DSP technology which is attempting to unseat the programmable DSP from the heart of tomorrow's mobile terminals

• Presents innovative new applications that are waiting to be discovered in the unique environment created when mobility meets signal processing

Targeting the latest microprocessor technologies for more sophisticated applications in the field of power system short circuit detection, this revised and updated source imparts fundamental concepts and breakthrough science for the isolation of faulty equipment and minimization of damage in power system apparatus. The Second Edition clearly describes key procedures, devices, and elements crucial to the protection and control of power system function and stability. It includes chapters and expertise from the most knowledgeable experts in the field of protective relaying, and describes microprocessor techniques and troubleshooting strategies in clear and straightforward language.

Electrical Engineering Design of High Performance Microprocessor Circuits This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High-Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, Motorola, and Toshiba. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth:
* Architectural constraints of CMOS VLSI design
* Technology scaling, low-power devices, SOI, and process variations
* Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units.
* Latches, clocks and clock distribution, phase-locked and delay-locked loops
* Register file, cache memory, and embedded DRAM design
* High-speed signaling techniques and I/O design
* ESD, electromigration, and hot-carrier reliability
* CAD tools, including timing verification and the analysis of power distribution schemes
* Test and testability
Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, processtechnologists, and researchers. It is also an essential text for VLSI design courses.

The Definitive Guide to the ARM Cortex-M0 is a guide for users of ARM Cortex-M0 microcontrollers. It presents many examples to make it easy for novice embedded-software developers to use the full 32-bit ARM Cortex-M0 processor. It provides an overview of ARM and ARM processors and discusses the benefits of ARM Cortex-M0 over 8-bit or 16-bit devices in terms of energy efficiency, code density, and ease of use, as well as their features and applications. The book describes the architecture of the Cortex-M0 processor and the programmers model, as well as Cortex-M0 programming and instruction set and how these instructions are used to carry out various operations. Furthermore, it considers how the memory architecture of the Cortex-M0 processor affects software development; Nested Vectored Interrupt Controller (NVIC) and the features it supports, including flexible interrupt management, nested interrupt support, vectored exception entry, and interrupt masking; and Cortex-M0 features that target the embedded operating system. It also explains how to develop simple applications on the Cortex-M0, how to program the Cortex-M0 microcontrollers in assembly and mixed-assembly languages, and how the low-power features of the Cortex-M0 processor are used in programming. Finally, it describes a number of ARM Cortex-M0 products, such as microcontrollers, development boards, starter kits, and development suites. This book will be useful to both new and advanced users of ARM Cortex devices, from students and hobbyists to researchers, professional embedded- software developers, electronic enthusiasts, and even semiconductor product designers.

Find hundreds of readily accessible tips for upgrading and tuning your PC inside this organized resource. Written by best-selling computer book author Kris Jamsa, you’ll get inside information and best practices on everything from system settings to adding and upgrading peripherals, and much more.

"The Pentium Chronicles" describes the architecture and key decisions that shaped the P6, Intel's most successful chip to date. As author Robert Colwell recognizes, success is about learning from others, and "Chronicles" is filled with stories of ordinary, exceptional people as well as frank assessments of "oops" moments, leaving you with a better understanding of what it takes to create and grow a winning product.

Microcontrollers are embedded into larger systems to provide benefits such as better performance, more features, better efficiency, lower costs and better dependability. This textbook introduces students to creating microcontroller-based embedded systems featuring an ARM Cortex-M CPU core.

An appendix covers how to measure the power and energy use on the FRDM-KL25Z board, including disconnecting the debug MCU to reduce power. Energy measurement using an ultracapacitor is also presented.

For use in ECE, EE, and CS departments.

This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as: * The policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers * Optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations * Design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors * State-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.