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Books > Professional & Technical > Energy technology & engineering > Electrical engineering

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Clock Generators for SOC Processors - Circuits and Architectures (Paperback, Softcover reprint of hardcover 1st ed. 2005) Loot Price: R2,948
Discovery Miles 29 480
Clock Generators for SOC Processors - Circuits and Architectures (Paperback, Softcover reprint of hardcover 1st ed. 2005): Amr...

Clock Generators for SOC Processors - Circuits and Architectures (Paperback, Softcover reprint of hardcover 1st ed. 2005)

Amr Fahim

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Loot Price R2,948 Discovery Miles 29 480 | Repayment Terms: R276 pm x 12*

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This book examines the issue of design of fully integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discre- time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized. Methods of generating low-spurious sampling clocks for discrete-time analog blocks are then examined. This includes sigma-delta fractional-N PLLs, Direct Digital Synthesis (DDS) techniques and non-conventional uses of PLLs. Design for test (DFT) issues as they arise in PLLs are then discussed. This includes methods of accurately measuring jitter and built-in-self-test (BIST) techniques for PLLs.

General

Imprint: Springer-Verlag New York
Country of origin: United States
Release date: November 2010
First published: 2005
Authors: Amr Fahim
Dimensions: 235 x 155 x 14mm (L x W x T)
Format: Paperback
Pages: 246
Edition: Softcover reprint of hardcover 1st ed. 2005
ISBN-13: 978-1-4419-5470-1
Categories: Books > Professional & Technical > Energy technology & engineering > Electrical engineering > General
Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
LSN: 1-4419-5470-8
Barcode: 9781441954701

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