ASIC/SoC Functional Design Verification - A Comprehensive Guide to Technologies and Methodologies (Hardcover, 1st ed. 2018)

This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.

General

Imprint:	Springer International Publishing AG
Country of origin:	Switzerland
Release date:	July 2017
First published:	2018
Authors:	Ashok B. Mehta
Dimensions:	235 x 155 x 23mm (L x W x T)
Format:	Hardcover
Pages:	328
Edition:	1st ed. 2018
ISBN-13:	978-3-319-59417-0
Categories:	Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General Promotions
LSN:	3-319-59417-6
Barcode:	9783319594170

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