Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design
|
Buy Now
SystemVerilog Assertions and Functional Coverage - Guide to Language, Methodology and Applications (Hardcover, 2014 ed.)
Loot Price: R5,503
Discovery Miles 55 030
|
|
SystemVerilog Assertions and Functional Coverage - Guide to Language, Methodology and Applications (Hardcover, 2014 ed.)
Expected to ship within 10 - 15 working days
|
This book provides a hands-on, application-oriented guide to the
language and methodology of both SystemVerilog Assertions and
SytemVerilog Functional Coverage. Readers will benefit from the
step-by-step approach to functional hardware verification, which
will enable them to uncover hidden and hard to find bugs, point
directly to the source of the bug, provide for a clean and easy way
to model complex timing checks and objectively answer the question
'have we functionally verified everything'. Written by a
professional end-user of both SystemVerilog Assertions and
SystemVerilog Functional Coverage, this book explains each concept
with easy to understand examples, simulation logs and applications
derived from real projects. Readers will be empowered to tackle the
modeling of complex checkers for functional verification, thereby
drastically reducing their time to design and debug.
General
Is the information for this product incomplete, wrong or inappropriate?
Let us know about it.
Does this product have an incorrect or missing image?
Send us a new image.
Is this product missing categories?
Add more categories.
Review This Product
No reviews yet - be the first to create one!
|
|
Email address subscribed successfully.
A activation email has been sent to you.
Please click the link in that email to activate your subscription.