Quantitative understanding of the parasitic capacitances and
inductances, and the resultant propagation delays and crosstalk
phenomena associated with the metallic interconnections on the very
large scale integrated (VLSI) circuits has become extremely
important for the optimum design of the state-of-the-art integrated
circuits. More than 65 percent of the delays on the integrated
circuit chip occur in the interconnections and not in the
transistors on the chip. Mathematical techniques to model the
parasitic capacitances, inductances, propagation delays, crosstalk
noise, and electromigration-induced failure associated with the
interconnections in the realistic high-density environment on a
chip will be discussed. A One-Semester Course in Modeling of VLSI
Interconnections also includes an overview of the future
interconnection technologies for the nanotechnology circuits.
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