Job Scheduling Strategies for Parallel Processing - 10th International Workshop, JSSPP 2004, New York, NY, USA, June 13, 2004, Revised Selected Papers (Paperback, 2005 ed.)

This volume contains the papers presented at the 10th Anniversary Workshop on Job Scheduling Strategies for Parallel Processing. The workshop was held in New York City, on June 13, 2004, at Columbia University, in conjunction with the SIGMETRICS 2004 conference. Although it is a workshop, the papers were conference-reviewed, with the full versions being read and evaluated by at least five and usually seven members of the Program Committee. We refer to it as a workshop because of the very fast turnaround time, the intimate nature of the actual presentations, and the ability of the authors to revise their papers after getting feedback from workshop attendees. On the other hand, it was actually a conference in that the papers were accepted solely on their merits as decided upon by the Program Committee. We would like to thank the Program Committee members, Su-Hui Chiang, Walfredo Cirne, Allen Downey, Eitan Frachtenberg, Wolfgang Gentzsch, Allan Gottlieb, Moe Jette, Richard Lagerstrom, Virginia Lo, Reagan Moore, Bill Nitzberg, Mark Squillante, and John Towns, for an excellent job. Thanks are also due to the authors for their submissions, presentations, and final revisions for this volume. Finally, we would like to thank the MIT Computer Science and Artificial Intelligence Laboratory (CSAIL), The Hebrew University, and Columbia University for the use of their facilities in the preparation of the workshop and these proceedings.

General

Imprint:	Springer-Verlag
Country of origin:	Germany
Series:	Lecture Notes in Computer Science, 3277
Release date:	April 2005
First published:	2005
Editors:	Dror Feitelson • Larry Rudolph • Uwe Schwiegelshohn
Dimensions:	235 x 155 x 17mm (L x W x T)
Format:	Paperback
Pages:	320
Edition:	2005 ed.
ISBN-13:	978-3-540-25330-3
Categories:	Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > Parallel processing Promotions
LSN:	3-540-25330-0
Barcode:	9783540253303

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