A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures (Paperback, Softcover reprint of the original 1st ed. 2003)

Despite five decades of research, parallel computing remains an exotic, frontier technology on the fringes of mainstream computing. Its much-heralded triumph over sequential computing has yet to materialize. This is in spite of the fact that the processing needs of many signal processing applications continue to eclipse the capabilities of sequential computing. The culprit is largely the software development environment. Fundamental shortcomings in the development environment of many parallel computer architectures thwart the adoption of parallel computing. Foremost, parallel computing has no unifying model to accurately predict the execution time of algorithms on parallel architectures. Cost and scarce programming resources prohibit deploying multiple algorithms and partitioning strategies in an attempt to find the fastest solution. As a consequence, algorithm design is largely an intuitive art form dominated by practitioners who specialize in a particular computer architecture. This, coupled with the fact that parallel computer architectures rarely last more than a couple of years, makes for a complex and challenging design environment. To navigate this environment, algorithm designers need a road map, a detailed procedure they can use to efficiently develop high performance, portable parallel algorithms. The focus of this book is to draw such a road map. The Parallel Algorithm Synthesis Procedure can be used to design reusable building blocks of adaptable, scalable software modules from which high performance signal processing applications can be constructed. The hallmark of the procedure is a semi-systematic process for introducing parameters to control the partitioning and scheduling of computation and communication. This facilitates the tailoring of software modules to exploit different configurations of multiple processors, multiple floating-point units, and hierarchical memories. To showcase the efficacy of this procedure, the book presents three case studies requiring various degrees of optimization for parallel execution.

General

Imprint:	Springer-Verlag New York
Country of origin:	United States
Series:	Series in Computer Science
Release date:	December 2012
First published:	2003
Authors:	Ian N. Dunn • Gerard G.L. Meyer
Dimensions:	235 x 155 x 6mm (L x W x T)
Format:	Paperback
Pages:	108
Edition:	Softcover reprint of the original 1st ed. 2003
ISBN-13:	978-1-4613-4658-6
Categories:	Books > Science & Mathematics > Mathematics > Numerical analysis Books > Computing & IT > General theory of computing > General Books > Computing & IT > Applications of computing > General Books > Science & Mathematics > Mathematics > Algebra > General Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Applied optics > General Promotions
LSN:	1-4613-4658-4
Barcode:	9781461346586

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