0
Your cart

Your cart is empty

Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design

Buy Now

Energy Efficient High Performance Processors - Recent Approaches for Designing Green High Performance Computing (Paperback, Softcover reprint of the original 1st ed. 2018) Loot Price: R3,466
Discovery Miles 34 660
Energy Efficient High Performance Processors - Recent Approaches for Designing Green High Performance Computing (Paperback,...

Energy Efficient High Performance Processors - Recent Approaches for Designing Green High Performance Computing (Paperback, Softcover reprint of the original 1st ed. 2018)

Jawad Haj-Yahya, Avi Mendelson, Yosi Ben-Asher, Anupam Chattopadhyay

Series: Computer Architecture and Design Methodologies

 (sign in to rate)
Loot Price R3,466 Discovery Miles 34 660 | Repayment Terms: R325 pm x 12*

Bookmark and Share

Expected to ship within 10 - 15 working days

This book explores energy efficiency techniques for high-performance computing (HPC) systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures (e.g. ARM). Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling (DVFS) for memory sub-systems.

General

Imprint: Springer Verlag, Singapore
Country of origin: Singapore
Series: Computer Architecture and Design Methodologies
Release date: 2019
First published: 2018
Authors: Jawad Haj-Yahya • Avi Mendelson • Yosi Ben-Asher • Anupam Chattopadhyay
Dimensions: 235 x 155 x 10mm (L x W x T)
Format: Paperback
Pages: 165
Edition: Softcover reprint of the original 1st ed. 2018
ISBN-13: 978-981-13-4184-7
Categories: Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General
LSN: 981-13-4184-2
Barcode: 9789811341847

Is the information for this product incomplete, wrong or inappropriate? Let us know about it.

Does this product have an incorrect or missing image? Send us a new image.

Is this product missing categories? Add more categories.

Review This Product

No reviews yet - be the first to create one!

Partners