Asynchronous System-on-Chip Interconnect (Paperback, Softcover reprint of the original 1st ed. 2002)

Asynchronous System-on-Chip Interconnect describes the use of an entirely asynchronous system-bus for the modular construction of integrated circuits. Industry is just awakening to the benefits of asynchronous design in avoiding the problems of clock-skew and multiple clock-domains, an din parallel with this is coming to grips with Intellectual Property (IP) based design flows which emphasise the need for a flexible interconnect strategy. In this book, John Bainbridge investigates the design of an asynchronous on-chip interconnect, looking at all the stages of the design from the choice of wiring layout, through asynchronous signalling protocols to the higher level problems involved in supporting split transactions. The MARBLE bus (the first asynchronous SoC bus) used in a commercial demonstrator chip containing a mixture of asynchronous and synchronous macrocells is used as a concrete example throughout the book.

General

Imprint:	Springer London
Country of origin:	United Kingdom
Series:	Distinguished Dissertations
Release date:	July 2013
First published:	2002
Authors:	John Bainbridge
Dimensions:	235 x 155 x 9mm (L x W x T)
Format:	Paperback
Pages:	139
Edition:	Softcover reprint of the original 1st ed. 2002
ISBN-13:	978-1-4471-1112-2
Categories:	Books > Computing & IT > General theory of computing > Systems analysis & design Books > Computing & IT > General theory of computing > Data structures Books > Computing & IT > Computer programming > Algorithms & procedures Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > General
LSN:	1-4471-1112-5
Barcode:	9781447111122

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