Design of High-Performance CMOS Voltage-Controlled Oscillators (Paperback, Softcover reprint of the original 1st ed. 2003)

Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results. The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.

General

Imprint:	Springer-Verlag New York
Country of origin:	United States
Series:	The Springer International Series in Engineering and Computer Science, 708
Release date:	October 2012
First published:	2003
Authors:	Liang Dai • Ramesh Harjani
Dimensions:	235 x 155 x 10mm (L x W x T)
Format:	Paperback
Pages:	158
Edition:	Softcover reprint of the original 1st ed. 2003
ISBN-13:	978-1-4613-5414-7
Categories:	Books > Professional & Technical > Energy technology & engineering > Electrical engineering > General Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Promotions
LSN:	1-4613-5414-5
Barcode:	9781461354147

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