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Generating Hardware Assertion Checkers - For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring (Hardcover, 2008 ed.) Loot Price: R2,810
Discovery Miles 28 100
Generating Hardware Assertion Checkers - For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line...

Generating Hardware Assertion Checkers - For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring (Hardcover, 2008 ed.)

Marc Boule, Zeljko Zilic

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Loot Price R2,810 Discovery Miles 28 100 | Repayment Terms: R263 pm x 12*

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Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity.

This is the first book that presents an under-the-hood view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.

General

Imprint: Springer-Verlag New York
Country of origin: United States
Release date: July 2008
First published: July 2008
Authors: Marc Boule • Zeljko Zilic
Dimensions: 235 x 155 x 17mm (L x W x T)
Format: Hardcover
Pages: 280
Edition: 2008 ed.
ISBN-13: 978-1-4020-8585-7
Categories: Books > Computing & IT > General theory of computing > General
Books > Computing & IT > Applications of computing > General
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LSN: 1-4020-8585-0
Barcode: 9781402085857

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