Cache and Interconnect Architectures in Multiprocessors (Paperback, Softcover reprint of the original 1st ed. 1990)

Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus based shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax) are currently limited to 32 processors. The fIrst goal of the workshop was to learn about the performance ofapplications on current cache-based systems. The second goal was to learn about new network architectures and protocols for future scalable systems. These protocols and interconnects would allow shared-memory architectures to scale beyond current imitations. The workshop had 20 speakers who talked about their current research. The discussions were lively and cordial enough to keep the participants away from the wonderful sand and sun for two days. The participants got to know each other well and were able to share their thoughts in an informal manner. The workshop was organized into several sessions. The summary of each session is described below. This book presents revisions of some of the papers presented at the workshop."

General

Imprint:	Springer-Verlag New York
Country of origin:	United States
Release date:	September 2011
First published:	1990
Editors:	Michel Dubois • Shreekant S. Thakkar
Dimensions:	235 x 155 x 16mm (L x W x T)
Format:	Paperback
Pages:	277
Edition:	Softcover reprint of the original 1st ed. 1990
ISBN-13:	978-1-4612-8824-4
Categories:	Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General
LSN:	1-4612-8824-X
Barcode:	9781461288244

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