On-Chip Networks (Paperback)

With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field. Table of Contents: Introduction / Interface with System Architecture / Topology / Routing / Flow Control / Router Microarchitecture / Conclusions

General

Imprint:	Morgan & Claypool Publishers
Country of origin:	United States
Series:	Synthesis Lectures on Computer Architecture
Release date:	July 2009
First published:	July 2009
Authors:	Natalie Enright • Li-Shiuan Peh
Dimensions:	235 x 187 x 7mm (L x W x T)
Format:	Paperback
Pages:	141
ISBN-13:	978-1-59829-584-9
Categories:	Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General
LSN:	1-59829-584-5
Barcode:	9781598295849

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