Analysis and Design of Networks-on-Chip Under High Process Variation (Hardcover, 1st ed. 2015)

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.

General

Imprint:	Springer International Publishing AG
Country of origin:	Switzerland
Release date:	December 2015
First published:	2015
Authors:	Rabab Ezz-Eldin • Magdy Ali El-Moursy • Hesham F. A. Hamed
Dimensions:	235 x 155 x 11mm (L x W x T)
Format:	Hardcover
Pages:	141
Edition:	1st ed. 2015
ISBN-13:	978-3-319-25764-8
Categories:	Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General Promotions
LSN:	3-319-25764-1
Barcode:	9783319257648

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