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Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design
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Analysis and Design of Networks-on-Chip Under High Process Variation (Hardcover, 1st ed. 2015)
Loot Price: R3,299
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Analysis and Design of Networks-on-Chip Under High Process Variation (Hardcover, 1st ed. 2015)
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Total price: R3,319
Discovery Miles: 33 190
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This book describes in detail the impact of process variations on
Network-on-Chip (NoC) performance. The authors evaluate various NoC
topologies under high process variation and explain the design of
efficient NoCs, with advanced technologies. The discussion includes
variation in logic and interconnect, in order to evaluate the delay
and throughput variation with different NoC topologies. The authors
describe an asynchronous router, as a robust design to mitigate the
impact of process variation in NoCs and the performance of
different routing algorithms is determined with/without process
variation for various traffic patterns. Additionally, a novel
Process variation Delay and Congestion aware Routing algorithm
(PDCR) is described for asynchronous NoC design, which outperforms
different adaptive routing algorithms in the average delay and
saturation throughput for various traffic patterns.
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